Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the largest pure FPGA engineering community in China. Introduction: When we conduct FPGA schematic and PCB design, we involve the pin definitions and package-related information of FPGA chips. This article provides relevant references for the Xilinx … Read more
EETOP focuses on chips and microelectronics, click on the blue text above to follow us. EETOP EETOP Chuangxin Network (Yite Chuangxin): A well-known domestic veteran electronic engineer community and semiconductor industry portal website (1.5 million members) www.eetop.cn bbs.eetop.cn blog.eetop.cn edu.eetop.cn EETOP compiled from allaboutcircuits.In the past month, the FPGA market has been thriving. In this … Read more
Welcome FPGA engineers to join the official WeChat technical group. With the diversification of demand, the functions of FPGAs have been further enhanced. Among them, high-speed transceivers, which were originally modules found only in high-end FPGAs, have become relatively common and even essential functional modules. The 10G line rate has also shifted from being supported … Read more
In-Depth Hardware Preparation and Planning Before starting the project, hardware selection and planning are crucial. In addition to considering the type of PCIe interface on the development board, attention must also be paid to its logic resources, storage bandwidth, etc. Taking Xilinx’s KCU105 development board as an example, it not only has a high-speed PCIe … Read more
Welcome FPGA engineers to join the official WeChat technical group. Fanout refers to the number of lower-level modules directly called by a module. If this value is too large, it directly manifests as a large net delay in FPGA, which is not conducive to timing convergence. Therefore, when writing code, one should try to avoid … Read more
1. Constraint Files There are three types of constraint files in Xilinx ISE FPGA design: User Constraint File (.UCF), Netlist Constraint File (.NCF), and Physical Constraint File (.PCF). These can achieve timing constraints, pin constraints, and area constraints. Users write UCF files during the design input phase, then the UCF file generates the NCF file … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us – FPGA Home, the best and largest community for pure FPGA engineers in China ISE version is 14.7 1. Clock IP Core (Clocking Wizard) Page one In the Clocking Features options box: (1) The Frequency synthesis option allows the output … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. In summary, the power-up modes of Xilinx FPGA can be divided into the following 4 types: Master Mode Slave Mode JTAG Mode (Debug Mode) System Mode … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China 1. Why Use Serdes Traditional source synchronous transmission separates clock and data. This works fine at lower rates (<1000M). However, this becomes problematic at higher rates. … Read more
Welcome FPGA engineers to join the official WeChat technical group. Overview of Xilinx 7 Series FPGAs Table of Contents Overview of Xilinx 7 Series FPGAs 1. Four Process Levels of Xilinx 2. Virtex, Kintex, Artix, and Spartan 3. Features of the 7 Series 4. Naming Convention of the 7 Series 5. Summary of 7 Series … Read more