FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

Fixed-point decimal division is much more complex than addition and multiplication, but the basic idea of the algorithm is still quite simple. Similar to integer division, the core idea of the algorithm is to convert the division operation into shift and subtraction operations. From a practical implementation perspective, there are generally two methods:

  • One is to keep the divisor unchanged and extend and shift the dividend.

  • The other is to keep the dividend unchanged and extend and shift the divisor.

The first method was introduced in my previous blog post about integer division, http://blog.chinaaet.com/justlxy/p/5100052068

This article adopts the second method, which is actually completely the same in basic idea as the first one. Due to time constraints, I won’t go into detail here; if I have time later, I will supplement this part of the algorithm’s principles… Interested readers can download a few related papers from IEEE for reading.

As with the previous routine, let’s enter the image mode! Haha!

First is qdiv.v:

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

Then is the Testbench file:

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

The RTL view is too long to post clearly, so I won’t include it.

Below is the ActiveHDL script file:

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

The simulation waveform diagram of ActiveHDL is as follows:

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

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