In this article, we learned how to customize Linux using PetaLinux and created a boot file for the SD card. This issue introduces how to configure PetaLinux to generate a Linux image file that boots from QSPI Flash. Copying the PetaLinux Project If we want to keep the PetaLinux project that boots from the SD … Read more
Authors:Tao Qingping, Shang Guoqing, Zhu QingAffiliation:1. China Electronics Technology Group Corporation, the 58th Research Institute, Wuxi, Jiangsu 214035.Abstract:With the popularity of SoC chip design, the demand for various IP designs is also increasing. The challenge for IC design engineers and verification engineers is how to quickly and accurately verify the correctness of these IP functions. … Read more
Follow and star our official account for exciting content Source: https://blog.csdn.net/weixin_39847099/article/details/111802365Organized by: ZYNQ | Xiao Mo The JTAG Configuration Process of Zynq When first learning Zynq, I believe everyone, like me, follows the usual practice of opening the Vivado software, setting up the programmable logic (PL) part of Zynq, exporting the hardware deployment, then opening … Read more
Welcome FPGA engineers to join the official WeChat technical group. This article mainly introduces the configuration modes of Xilinx FPGAs, including Master/Slave mode, Serial/SelectMAP mode, JTAG mode, etc. Among them, the 7 series only has the Logic part, and all configuration-related function pins are connected to specific banks on the FPGA side; the Zynq 7000 … Read more
Welcome FPGA engineers to join the official WeChat technical group Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China The Xilinx PYNQ framework enables comprehensive support and integration of the Python language and runtime in the Zynq product family. By leveraging the productivity advantages of … Read more
Welcome FPGA engineers to join the official WeChat technical group ClickBlue TextFollow us at FPGA Home – the best and largest pure engineer community in China for FPGA This article mainly introduces the power design for Xilinx FPGA, covering types of power supply, voltage requirements, power consumption needs, power-up and power-down timing requirements, and common … Read more
Commercial off-the-shelf FPGAs are considered the only way to meet the increasing processing power demands of space applications. Due to their sensitivity to multi-bit flips, specialized design hardening techniques are required to address single particle effects in space applications. A fault-tolerant technology framework based on three levels: user logic layer, configuration memory layer, and control … Read more
Based on the ZYNQ platform, an embedded Linux operating system can be deployed. If you need to configure a static IP address, you can use the following methods. Method 1: Configure via Petalinux If the Linux system is created using Petalinux, you can configure the static IP address through Petalinux. Navigate to the Petalinux project … Read more
Introduction to Timers In ZYNQ embedded systems, timer resources are abundant. Each Cortex-A9 processor has its own independent 32-bit private timer and a 32-bit watchdog timer, while both CPUs share a single 64-bit Global Timer Counter (GTC). System Block Diagram Global Timer (GTC) The Global Timer is a 64-bit incrementing counter with an automatic increment … Read more
[Conclusion] General IO cannot be directly used as a clock input for PLL; dedicated clock pins can be used instead. General IO can be connected to the PLL clock input through a BUFG, but the PLL settings must be modified to select “No Buffer” for the input clock option. The specific internal layout can be … Read more