Abstract: Considering the characteristics and requirements of smart homes, this study adopts a combination of wireless ZigBee sensor networks and power line communication technology. This approach not only realizes the low power consumption, low cost, and flexible networking capabilities of ZigBee, but also utilizes existing household power lines as communication channels through power line carrier … Read more
RISC-V is an instruction set architecture (ISA) for microprocessors, and people’s opinions about it are polarized. This is especially true given the apparent competition between the ARM and RISC-V camps. This makes sense. RISC-V and ARM represent fundamentally different philosophies on how to design RISC chips. RISC-V has a long-term view that emphasizes simplicity, avoiding … Read more
Previously, we discussed the on-chip interconnect bus, but having just the bus is not enough; we also need on-chip bus protocol support. Only with the protocol can we operate the registers accurately. When it comes to on-chip bus protocols, there are many, such as the AMBA bus used by ARM, the Wishbone bus by Silicore, … Read more
1 I2C Bus The programming related to I2C mainly involves two situations: ARM chips with dedicated controllers and microcontroller chips without controllers. For ARM chips with controllers, operations are performed based on the data manual by setting the corresponding registers (control registers, status registers, etc.); however, for microcontroller chips without controllers, I2C protocol needs to … Read more
Recently, Arm officially released the TCS23 (Total Compute Solutions 23) platform along with corresponding IP products, including the Cortex-X4, A720, A520 CPUs based on the Armv9 architecture, and the latest Immortalis-G720, which is a new IP based on Arm’s fifth-generation GPU microarchitecture, along with an updated DSU. Undoubtedly, these IPs will be the focus of … Read more
Click the above Computer Enthusiasts to follow us When it comes to ARM, everyone should be very familiar with it. It does not produce chips; it only provides an idea for chip design, including native core IP and the ARMv instruction set. Among them, the core IP includes the well-known Cortex-A78 and Cortex-X1. Chip manufacturers … Read more
1. What do T, D, M, and I stand for in ARM7TDMI? Answer: These four letters represent a characteristic of ARM: T: High-density 16-bit Thumb instruction set extension D: Supports on-chip debugging M: 64-bit multiplication instruction I: Includes embedded ICE hardware simulation module 2. Quick Knowledge Summary: ARM7 adopts a 3-stage pipeline, while ARM9 adopts … Read more
One Introduction Often, programs run without an operating system, which is known as bare-metal operation and cannot run directly in Linux. Therefore, alternative methods must be used for analysis. Taking a CTF problem as an example, we will learn about analyzing bare-metal programs on the ARM architecture. Two Analysis Program address: https://dn.jarvisoj.com/challengefiles/confusedARM.hex.f4e616545ff1a18526b9d1c90ea648ff This program is … Read more
Click the blue "Arm Selected" in the upper left corner and select "Set as Star" Note: This article primarily discusses the ARMV8-aarch64 architecture, gicv3, and Linux kernel 5.14 by default. Consideration: Have you ever thought about a scenario where a high-priority interrupt preempts another interrupt that is currently being processed? This is known as interrupt … Read more
ARM defines two low-power interfaces for low power control handshakes, namely Q-Channel and P-Channel. The Q-Channel was discussed previously in “SoC Design Power Consumption – Q Channel“. The Q-Channel is relatively simpler than the P-Channel, as it only controls two states: on and off. This is fine for handshakes controlling clocks, but insufficient for handshakes … Read more