Here are the results from the past two days, implementing FPGA fixed-point decimal calculation in Verilog. There will be N parts, including addition, multiplication, division, square root, square, etc. Currently, addition and multiplication have been debugged, while division, square root, and square are not yet completed. Due to time constraints, this blog post will directly … Read more
Fixed-point decimal division is much more complex than addition and multiplication, but the basic idea of the algorithm is still quite simple. Similar to integer division, the core idea of the algorithm is to convert the division operation into shift and subtraction operations. From a practical implementation perspective, there are generally two methods: One is … Read more
The fi function supports six rounding modes, which can be observed through the code snippets shown in the following three images. The input data x is a double-precision floating-point number, and it is to be converted into a fixed-point number with a sign bit of 1, a word length of 4, and a fractional length … Read more
Previous articles mainly focused on the Processing System (PS) of the Zynq SoC, including: Using MIO and EMIO The interrupt structure of Zynq SoC Zynq private timers and watchdogs The triple timer counter (TTC) of Zynq SoC However, from a design perspective, the truly exciting aspect of the Zynq SoC is creating applications that utilize … Read more