Mr. Big Cat says: Translation of Chapter 13 from the compilation “RFSoC-Book” is detailed in the first article of this series. “An open-source masterpiece, ‘Software Defined Radio Based on Zynq UltraScale+ RFSoC’” Mr. Big Cat, WeChat public account: Mr. Big Cat’s Little Bookcase, an open-source masterpiece, ‘Software Defined Radio Based on Zynq UltraScale+ RFSoC’ For … Read more
*To obtain the complete reference guide,please scan the QR code at the end of the document to download it.. AMD Adaptive Computing documentation is organized according to a set of standard design processes to help you find content relevant to your current development tasks. You can access the AMD Versal™ Adaptive SoC design process on … Read more
This article is authored by Xilinx Engineer Hank Fu In the office, there is a VCK190 board running in SD boot mode, which can enter Linux. However, now that we are working from home, we cannot change the boot mode of the VCK190 board. We need to run a Standalone program. Therefore, we hope that … Read more
Author: Xilinx Engineer Hank Fu The office has a VCK190 board running in SD boot mode, which can boot into Linux. However, now that we are working from home, we cannot change the boot mode of the VCK190 board. We need to run a Standalone program. Therefore, we hope that like MPSoC, when the Versal … Read more
1. Overview Xilinx FPGAs starting from the 7 series have on-chip Advanced Encryption Standard (AES) decryption logic, providing a high level of design security. Encrypted Xilinx FPGA designs cannot be copied or reverse-engineered for other FPGAs.The Xilinx FPGA responsible for encryption uses an AES system consisting of software-based bitstream encryption and on-chip bitstream decryption, with … Read more
Xilinx® Kria KV260 Vision AI Starter Kit, is a member of the Kria Adaptive System Module (SOM) and Developer Kit product family. It consists ofK26 System Level Module(SOM), carrier card, and cooling solutions. The SOM on the kit is based on theZynq UltraScale+ MPSoC architecture paired with4 GB DDR4 memory, enabling rapid development of hardware-accelerated … Read more
Why is it called “Xilinx HLS”? It is said that Altera’s HLS is somewhat different. 1 HLS Design The names of Xilinx’s HLS tools vary; I recall “Vivado HLS” and “Vitis HLS”. The version of the tool I used is 2024.2, and this version of the HLS tool is called “Vitis”. Vitis 2024.2 is a … Read more
Please ensure that you have correctly installed the required tools and that your environment meets the requirements. Hardware Requirements This tutorial corresponds to the Versal ACAP VCK190 and VMK 180 evaluation boards. The examples in this tutorial have been tested using the VCK190 ES1 evaluation board. To use this tutorial, you will need the following … Read more
In this article, we implement a design for interconnecting the ZYNQ FPGA PS side processor with the PL side registers, using the Vitis program on Windows to control the FPGA PS side ARM to read and write the PL side registers. 1. Generate the hardware logic on the PL side Taking the ZU7EV series as … Read more
Q: Memory write error at 0x0, Cortex-A53 #0: EDITR not ready A: The first step is to clean the program and rebuild to see if the issue can be resolved. If not, close Vitis and reopen it to check if the problem persists. If the issue remains, create a new app; this usually resolves the … Read more