Introduction — In FPGA-based image acquisition and display systems, large-capacity and high-speed memory is often required. Among various random access memory devices, SDRAM is an ideal choice due to its low cost, small size, high speed, and large capacity. However, the control logic of SDRAM is quite complex, and the timing requirements are very strict, … Read more
In FPGA design, frequency division is often required. For even frequency division, the code is relatively simple; the clock is inverted when the counter reaches half of the division factor, thus completing the even frequency division.For odd frequency division, the approach is slightly more complex. First, two temporary frequency division variables need to be defined: … Read more
Introduction This article is dedicated to those who have just embarked on the embedded path. Here, I briefly document my learning experiences and some insights I have gained along the way, hoping to help beginners avoid unnecessary detours. The image above shows a corner of the laboratory where I have worked and studied, looking quite … Read more
This is also a series of articles, stemming from previous discussions with fans in the comments about the efforts made abroad for FPGA development or entry-level engagement. Each article will introduce a specific FPGA development board, focusing on the development methods prepared for the board (which are quite different from those in China). Today’s main … Read more
The Artix 7 series FPGA provides many DSP hardware units that can be configured for floating-point operations.In the Vivado IP configuration interface, the clock cycle for the module can be selected, and data can be read out after a specified number of clock cycles.The Floating Point IP resource user manual from Vivado.However, it is somewhat … Read more
Introduction During the FPGA development process, it is common to encounter situations where data needs to be cached for later use. Typically, there are two solutions: RAM and FIFO. However, using FIFO has two limitations: There is a fixed delay of at least 3 clock cycles between FIFO output and input, and it cannot be … Read more
(Source: design-reuse) Recently, the American semiconductor startup Zero ASIC announced the launch of the world’s first open standard eFPGA IP product, Platypus. According to them, Platypus is the first and only commercial eFPGA IP product with the following features: a 100% open and standardized FPGA architecture, a 100% open-source FPGA bitstream format, and 100% open-source … Read more
Click the blue textto follow us With thedevelopment ofLLM, the importance of accelerators capable of efficiently processingLLM computations has become increasingly prominent. This article discusses the necessity ofLLM accelerators and provides a comprehensive analysis of the main hardware and software features of currently available commercialLLM accelerators. Based on this, it proposes development ideas and future … Read more
In this era of the Internet of Things, how can we quickly capture rapidly changing signal data? There is a golden partner solution: the RK3588J is a high-performance processor based on Rockchip RK3588, combined with the flexibility of FPGA, the combination of the two can achieve many innovative applications in the AI era. In terms … Read more
