Don’t let these misconceptions hinder your growth curve At two in the morning, the lights in the lab are still on. You stare at the flashing timing error messages on the screen, having modified the Verilog code for the 17th time, yet the development board remains silent as a stone. The coffee beside you has … Read more
In the embedded field, FPGAs are a very important type of device. Today, AMD announced the 40th anniversary of the first commercial Field Programmable Gate Array (FPGA) being introduced. What stories lie behind FPGAs, what is the current development situation domestically and internationally, and can domestic FPGAs take the lead? From Replacing ASICs to Edge … Read more
FPGA (Field Programmable Gate Array) development is a complex process that involves multiple steps and stages. Below is the basic process of FPGA development: Function Definition/Device Selection: Before system design, it is essential to conduct feasibility studies, system design, and selection of FPGA chips. System engineers weigh various aspects such as system specifications, complexity, working … Read more
01 — Rocky Linux Plans to Support RISC-V Rocky Linux has officially announced plans to support RISC-V in the upcoming release of Rocky Linux 10, aligning with the Fedora RISC-V community. Supported Platforms： ✅ StarFive VisionFive 2：Fully supported, ready to use with the standard RHEL10 kernel. ✅ QEMU：Provides full support, suitable for testing and evaluation. … Read more
This year marks the 40th anniversary of the first commercially available Field-Programmable Gate Array (FPGA), which introduced the concept of reprogrammable hardware. By creating “hardware as flexible as software,” the reprogrammable logic of FPGAs has fundamentally changed the landscape of semiconductor design. For the first time in history, developers could design chips and redefine their … Read more
Environment: Vivado 2023.2 FPGA Model: XCVU47P FPGA Project Overview: The main control logic of the FPGA uses four AXI interfaces with on-chip HBM resources (supporting up to 16 groups); Main clock domain frequency: 250MHz HBM interface clock frequency: 450MHz Problem: As the number of logic resources and BRAM used in the design increases, timing closure … Read more
Mean filtering is a fundamental digital signal processing technique commonly used for image and signal denoising. This article will detail how to implement a simple yet efficient mean filter using the Verilog hardware description language. Basic Principles of Mean Filtering The core idea of mean filtering is to replace the value of a pixel with … Read more
Table of Contents Hello-FPGA CoaXPress 2.0 Host FPGA IP Core Linux Demo 4 1 Description 4 2 Device Connection 7 3 VIVADO FPGA Project 7 4 Debugging Instructions 10 Figure 1-1 Document Directory 4 Figure 1-2 VIVADO Project Directory Structure 5 Figure 1-3 SDK Project Directory Structure 5 Figure 1-4 Device Tree Information 6 Figure … Read more
Welcome to leave a message, I will reply to each message on the same day, and any errors in the article will be updated in the reply. The design is conducted in the Vivado 2018.3 environment, with specific code and detailed line-by-line comments at the end. This is a dynamic display design for FPGA seven-segment … Read more
Introduction As medical technology continues to evolve, endoscopic examination has become an indispensable method in the diagnosis and treatment of various diseases. From screening gastrointestinal diseases to observing pulmonary lesions and diagnosing urinary system disorders, endoscopes can penetrate deep into the human body, providing doctors with intuitive internal tissue images, significantly enhancing diagnostic accuracy and … Read more