FPGA Timing Description Language

FPGA Timing Description Language

First, let’s clarify what is meant by “timing” here, which refers to the logical relationships of a set of signals, rather than timing parameters like steptime and holdtime. If you want to understand why this article exists, please refer to the series “Where is FPGA Going” and “What HLS Does FPGA Need”. Here, we focus … Read more

Recommended Books for Digital IC Design

Recommended Books for Digital IC Design

IC design, or Integrated Circuit Design, is a discipline of electronic engineering and computer engineering, mainly focusing on the design of integrated circuits (IC) using specialized logic and circuit design techniques. This article mainly introduces classic books on digital IC design. Let’s follow along to learn more. 1. ‘Advanced Digital Design with Verilog HDL’ This … Read more

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

FPGA Fixed-Point Decimal Calculation (Verilog Version) Part 3

Fixed-point decimal division is much more complex than addition and multiplication, but the basic idea of the algorithm is still quite simple. Similar to integer division, the core idea of the algorithm is to convert the division operation into shift and subtraction operations. From a practical implementation perspective, there are generally two methods: One is … Read more

Choosing Domestic FPGA Chips: Alternatives to Xilinx

Choosing Domestic FPGA Chips: Alternatives to Xilinx

Recently, our company has been preparing for the FPGA localization plan and conducting market research. We have also arranged discussions with market engineers from several domestic FPGA manufacturers.Regarding FPGA, I consider myself a latecomer. After graduating, I worked on MCU development for about a year, and later, due to project needs, I started to engage … Read more

Xilinx Verilog Syntax Tips

Xilinx Verilog Syntax Tips

Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. Comprehensive Attributes In the Vivado Design Suite, the Vivado synthesis can synthesize various types of attributes. In most cases, these attributes have the same syntax and … Read more

Using PCIe XDMA in Xilinx FPGA

Using PCIe XDMA in Xilinx FPGA

In-Depth Hardware Preparation and Planning Before starting the project, hardware selection and planning are crucial. In addition to considering the type of PCIe interface on the development board, attention must also be paid to its logic resources, storage bandwidth, etc. Taking Xilinx’s KCU105 development board as an example, it not only has a high-speed PCIe … Read more

Basics of Xilinx FPGA Constraints

Basics of Xilinx FPGA Constraints

1. Constraint Files There are three types of constraint files in Xilinx ISE FPGA design: User Constraint File (.UCF), Netlist Constraint File (.NCF), and Physical Constraint File (.PCF). These can achieve timing constraints, pin constraints, and area constraints. Users write UCF files during the design input phase, then the UCF file generates the NCF file … Read more

Xilinx FPGA Learning Notes

Xilinx FPGA Learning Notes

Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. 1. Timing Design Method 1: Implementing through state machines, controlling the FPGA with Verilog to make it fast when necessary and slow otherwise. Method 2: Running … Read more