Xilinx FPGA SelectIO Resources

Welcome FPGA engineers to join the official WeChat technical group.

Clickthe blue textto follow us at FPGA Home – the largest and best pure FPGA engineer community in China.

Xilinx FPGA SelectIO Resources

This article mainly introduces the I/O resources on the PL side of Xilinx FPGA, which currently includes three types: HP, HR, and HD. Different architectures and packages of FPGAs have different types and quantities of I/O resources. When connecting peripherals, be sure to pay attention; for example, a 3.3V logic level cannot be directly connected to the HP bank, and its VCCO power supply voltage cannot be directly connected to 3.3V.

UltraScale architecture-based devices provide various I/O offerings: High-performance (HP), high-density (HD), and high-range (HR) I/O banks. Generation Form Factor.

  • The HR I/O banks are designed to support a wider range of I/O standards with voltages up to 3.3V.

  • The HP I/O banks are designed to meet the performance requirements of high-speed memory and other chip-to-chip interfaces with voltages up to 1.8V.

  • The HD I/O banks are designed to support low-speed interfaces.

The 7 series FPGAs offer both high-performance (HP) and high-range (HR) I/O banks.

Kintex UltraScale and Virtex UltraScale families have high-performance I/O banks (HP I/Os) and high-range I/O banks (HR I/Os) with corresponding logic resources.

The Virtex UltraScale+ family only has high-performance I/O banks (HP I/Os) with the corresponding logic resources. These I/O banks also have enhanced MIPI D-PHY support capabilities.

The Zynq UltraScale+ MPSoC and Kintex UltraScale+ FPGA families have high-performance I/O banks (HP I/Os) with enhanced MIPI D-PHY abilities and the corresponding logic resources. They also have high-density I/Os (HD I/Os) with corresponding logic resources.

1. HP/HR

Xilinx FPGA SelectIO Resources

UltraScale devices support many of the same features supported in 7 series devices. However, there are some useful new features, along with changes to several existing features. These new features and changes include:

  • Each I/O bank contains 52 SelectIO interface pins. In some devices, there are some HR I/O mini-banks containing 26 SelectIO pins, each with their own independent power supply and VREF pin. (HR bank supports a mini-bank with only 26 I/Os)

  • Support for pseudo-open-drain logic standards (POD). (Supports DDR4 POD logic, but only HP bank supports it)

  • Series output termination control is available in HP I/O banks for improved signal integrity and ease of board design. (HP bank has series termination)

  • Internal VREF level scan (HP I/O banks only). One dedicated external VREF pin per bank. (Each HP bank has a VREF)

  • Pre-emphasis is available for the DDR4 standard in HP I/O banks and the LVDS TX standard in HP/HR I/O banks. Pre-emphasis reduces inter-symbol interference and minimizes the effects of transmission line losses. (HP bank’s POD and HP/HR bank’s LVDS TX have pre-emphasis functionality)

  • Linear equalization on VREF-based receivers (in HP I/O banks) and differential receivers (in both HP and HR I/O banks) is available to overcome high-frequency losses through the transmission channel. (There is linear equalization functionality)

  • Receiver offset cancellation is available for some I/O standards to compensate for process variations (HP I/O banks only).

  • Digitally controlled impedance (DCI) is only available in HP I/O banks. DCI uses only one reference resistor per bank, 240Ω to GND on the VRP pin. The values of the driver or input termination are determined by the OUTPUT_IMPEDANCE and on-die termination (ODT) attributes, respectively.

  • VCCAUX_IO only supports a nominal voltage level of 1.8V.

  • A SLEW value of MEDIUM is supported in HP I/O banks.

  • The DCITERMDISABLE port can control both DCI and non-DCI on-die input termination features in HP I/O banks.

  • Where applicable, asserting IBUFDISABLE causes the input to the interconnect logic to be a 0. This is different from the resulting 1 after asserting IBUFDISABLE in 7 series devices.

  • The bit slice is effectively a physical layer (PHY) block that replaces and enhances the functionality of the Component mode primitives. This PHY block gives tighter control over timing and provides new features enabling higher data rate reception in UltraScale devices.

  • MIPI D-PHY transmitter and receiver functions are supported in the HP I/Os specific to the Virtex UltraScale+ devices, Kintex UltraScale+ devices, and Zynq UltraScale+ MPSoCs.

2. HD
High-density (HD) I/O banks are SelectIO resources designed to support a wide range of I/O standards with voltages ranging from 1.2V to 3.3V. HD I/Os are optimized for single-ended, voltage-referenced, and pseudo-differential I/O standards operating at data rates of up to 250 Mb/s. Limited support for true differential inputs (with external termination) is also available to support LVDS and LVPECL clock inputs. HD I/Os also contain interface logic including registers and static delay lines to support asynchronous, system synchronous, and clock-based source synchronous interfaces.

Xilinx FPGA SelectIO Resources

Every HD I/O bank contains 24 I/O pins. When defined as single-ended standards, HD I/O pins support input, output, and bidirectional operating modes. Paired I/O pins can be used to support differential standard functionality. For pseudo-differential standards, like DIFF_SSTL15, input, output, and bidirectional support is available. True differential standards, like LVDS_25, can only function as an input buffer.

For detailed information, please refer to the User Guides of different series of I/O resources, as follows:

UG471: 7 Series FPGAs SelectIO Resources User Guide

UG571: UltraScale Architecture SelectIO Resources User Guide

and the Data Sheets of each device.

Xilinx FPGA SelectIO Resources

Welcome FPGA, embedded, signal processing, and other engineers to follow our public account.

Xilinx FPGA SelectIO Resources

The largest FPGA WeChat technical group in the country

Welcome everyone to join the national FPGA WeChat technical group, which has tens of thousands of engineers, a group of engineers who love technology. FPGA engineers here help each other and share knowledge, creating a strong technical atmosphere!Hurry up and invite your friends to join!!

Xilinx FPGA SelectIO Resources

Press and hold to join the national FPGA technical group.

FPGA Home Component City

Advantageous component services, please contact the group owner: Jin Juan, email: [email protected] Welcome to recommend to purchasing

ACTEL, AD part advantageous ordering (operating the full series):

Xilinx FPGA SelectIO Resources

XILINX, ALTERA advantageous stock or order (operating the full series):

Xilinx FPGA SelectIO Resources

(The above devices are some models, for more models please consult group owner Jin Juan)

Service philosophy: FPGA Home Component City aims to facilitate engineers to quickly and conveniently purchase components. After years of dedicated service, our customer service is spread across large domestic listed companies, military research units, and small and medium enterprises. Our biggest advantage is emphasizing the service-first philosophy and achieving fast delivery and competitive prices!

Directly operated brands: Xilinx ALTERA ADI TI NXP ST E2V, Micron and more than a hundred component brands, especially good at components subject to US sanctions against China.We welcome engineer friends to recommend us to purchasing or consult us directly!We will continue to provide the best service in the industry!

Xilinx FPGA SelectIO Resources

Official thanks to brands in the FPGA technical group: Xilinx, Intel (Altera), Microsemi (Actel), Lattice, Vantis, Quicklogic, Lucent, etc.

Related posts

  1. Introduction to PMOD Interface on Xilinx FPGA
  2. Xilinx 7 Series FPGA Pin Definition Design Guide
  3. Choosing Domestic FPGA Chips: An Overview of Alternatives to Xilinx
  4. Xilinx 7 Series FPGA SelectIO Overview
  5. Xilinx 7 Series FPGA High-Speed Transceiver RX Receiver Introduction
  6. Power Design for Xilinx FPGA
  7. Xilinx 7 Series FPGA Selection Guide
  8. In-Depth Study of Xilinx High-Speed Transceivers (Serdes)
  9. Configuring Common Xilinx IP Cores
  10. Methods to Solve High Fanout in Xilinx
  11. Comparison of the Latest FPGAs from Xilinx, Intel, and Lattice
  12. Detailed Explanation of Xilinx RapidIO Core
  13. Dedicated Clock Pins and Resources in Xilinx FPGAs
  14. Basic Concepts of Xilinx 7 Series FPGA High-Speed Transceivers GTX/GTH
  15. Summary of Xilinx FPGA Constraint Design and Timing Analysis
  16. The Value of Python Productivity: Analyzing the Cutting-Edge Advantages of Xilinx Zynq
  17. Xilinx FPGA Encryption Solutions

Leave a Comment