Debugging Protocol SWD as a Replacement for JTAG on ARM Architecture

Debugging Protocol SWD as a Replacement for JTAG on ARM Architecture

For embedded developers and hardware hackers, JTAG is the standard for debugging and accessing microprocessor registers. This protocol has been in use for many years and is still used today. The JTAG debugging interface requires VCC, GND power signals, and four debugging signals: TMS, TCK, TDI, and TDO. Additionally, TRST and RESET reset signals and … Read more

Introduction to JTAG Interface in Embedded C Development

Introduction to JTAG Interface in Embedded C Development

1. Definition: – JTAG (Joint Test Action Group) is a standard for testing and debugging integrated circuits, widely used in embedded systems development. 2. Purpose: – To debug, test, and program embedded systems, allowing developers to inspect and manipulate the internal state of the processor. 3. Components: – The Test Access Port (TAP) controller manages … Read more

Interface Standard JTAG in Embedded Debugging

Interface Standard JTAG in Embedded Debugging

Hello everyone, I am Pi Zi Heng, a serious tech enthusiast. Today, I will talk about the interface standard JTAG in embedded debugging. In embedded development, it is inevitable to simulate and debug code, especially when the application logic becomes complex to a certain extent. It is common to introduce some logical bugs while writing … Read more

MCU Testing and External NOR Programming Using JTAG_BSDL – LPC1857 Example

MCU Testing and External NOR Programming Using JTAG_BSDL - LPC1857 Example

1. Introduction Previously, we sharedhttps://mp.weixin.qq.com/s/BeL6UbSg2HI9qKemZugOhw?token=1054074707&lang=zh_CN the article titled“Low-Cost Learning FPGA Based on“Mining Board”” which usesJTAG boundary scan for quick pin correspondence reverse engineering.. Not only forFPGAs, but we can also useJTAG for boundary scan testing inMCUs, provided that the corresponding chip supports this feature and the manufacturer providesBSDL files. Here, we will demonstrate using theLPC1857 … Read more

Pull-Up and Pull-Down Signals in JTAG

Pull-Up and Pull-Down Signals in JTAG

1 Description in the JTAG Standard Latest JTAG standard: IEEE_std_1149.1-2001 Figure 1 JTAG Principle 1.1 TMS TMS is the start enable signal (Standard PAGE-11), pull-up: 1.2 TCK TCK is the clock signal (Standard PAGE-9) effective on the rising or falling edge, can be pulled up or pulled down, depending on specific device requirements: 1.3 TDI … Read more

Understanding JTAG and Its Alternatives

Understanding JTAG and Its Alternatives

This article mainly introduces the terms related to JTAG that are easily confused: JTAG JTAG (Joint Test Action Group): In the early application of chips, different manufacturers had different testing methods for chips, making the joint testing of chips and boards very difficult. A unified testing method was needed to solve this problem. The JTAG … Read more