ASIC design

Design and Verification of FPGA Programmable Logic Element Based on Sense-Switch pFLASH

by
Design and Verification of FPGA Programmable Logic Element Based on Sense-Switch pFLASH

Content Introduction Abstract: This paper proposes a programmable logic element (PLE) based on Sense-Switch type pFLASH technology. By programming the Sense-Switch type pFLASH, all three-input lookup table (LUT3) functions, some LUT4 functions, latch functions, and D flip-flop (DFF) functions with enable and reset capabilities are realized. Because the PLE uses a method called Combinational Operation … Read more

The Evolution Path of Future CPU Processor Technology

by
The Evolution Path of Future CPU Processor Technology

This article is excerpted from “2022 Research Framework for Domestic Server CPUs“. In the post-Moore’s Law era, the performance benefits brought by the improvement of process technology are already very limited. The Dennard Scaling law constraints have led to a sharp increase in chip power consumption, and the cost of transistors has risen instead of … Read more

Event-Driven Synchronized Readout Prototype ASIC Chip for HFRS-TPC

by
Event-Driven Synchronized Readout Prototype ASIC Chip for HFRS-TPC

Paper Information: EDIMS: an event-driven internal memory synchronized readout prototype ASIC chip developed for HFRS-TPC Yang, M., Qian, Y., Pu, T., Lu, W., Sun, Z., Zhao, H., Zhang, J., & Liu, Z. DOI:10.1007/s41365-023-01341-w Article Highlights HFRS is a radioactive secondary beam separator at China’s high-current heavy ion accelerator facility HIAF. Several high-count-rate TPC detectors are … Read more

The Future of AI Chips: Not Necessarily GPUs

by
The Future of AI Chips: Not Necessarily GPUs

Source: Semiconductor Industry Review Original Author: Feng Ning In the layout of artificial intelligence computing architecture, the collaborative working model of CPUs and acceleration chips has become a typical AI deployment solution. The CPU plays the role of providing basic computing power, while the acceleration chips are responsible for enhancing computing performance to assist algorithms … Read more

How MEMS Sensor Chips Are Manufactured

by
How MEMS Sensor Chips Are Manufactured

For a wealth of sensor knowledge and industry reports, please reply with the keyword 【资料下载】 in the public account dialog to obtain materials for viewing.《Over 100 Professional Knowledge Materials on Sensors, There’s Always One for You~》 Follow me here 👇,Remember to click the menu bar in the top right corner ••• Set as Star ⭐ … Read more

Summary of Multi-Clock Domain Processing Methods in IC Design

by
Summary of Multi-Clock Domain Processing Methods in IC Design

In ASIC or FPGA system design, we often encounter the issue of data transmission across multiple clock domains, and timing issues become increasingly severe as the system grows more complex. Cross-clock domain processing technology is a crucial part of IC design. We need to learn and apply some common processing methods to enhance the stability … Read more

The Viability of FPGA Compared to CPU, GPU, and ASIC

by
The Viability of FPGA Compared to CPU, GPU, and ASIC

In recent years, the concept of FPGA has become increasingly prevalent. For example, in Bitcoin mining, there are miners based on FPGA. Additionally, Microsoft previously stated that it would use FPGA to “replace” CPU in data centers, among other things. In fact, for professionals, FPGA is not unfamiliar; it has been widely used. However, most … Read more

Differences Between AI Chips and Traditional Chips

by
Differences Between AI Chips and Traditional Chips

The following content is organized from Zhihu: Author: Wang Peng Link:https://www.zhihu.com/question/285202403/answer/444253962First, let me answer the question, (1) There is a significant difference in performance compared to traditional chips, such as CPUs and GPUs. When executing AI algorithms, they are faster and more energy-efficient. (2) There is no difference in manufacturing processes; everyone is the same. … Read more

Summary of Low Power Design in ASIC Design + Book Recommendations

by
Summary of Low Power Design in ASIC Design + Book Recommendations

1. Low Power Design With the promotion of handheld portable devices, the issue of low power design has become increasingly important. Lower chip power consumption means longer usage time for portable devices, increased lifespan of chips due to reduced power consumption, better control of heat dissipation, and the ability to make devices smaller, among other … Read more

ASIC Chip Design Enhances Safety and Reliability of Electronic Detonators

by
ASIC Chip Design Enhances Safety and Reliability of Electronic Detonators

On December 22, 2023, the “2023 Forum on High-Quality Development of the Civil Explosives Industry” was grandly held in Nanjing, Jiangsu Province, organized by the China Explosive Materials Industry Association. Zhu Jianyong, General Manager of Rongguisi Chuang, was invited to give a keynote speech titled “Enhancing the Safety and Reliability of Electronic Detonators Based on … Read more