The following question was asked by a VIP student from the Cortex-A72 training camp: After completing the single-core CPU PR, how do I output the data to TOP for multi-core hierarchy integration? Answer: After completing the single-core CPU, you need to output library files such as SDC, DEF, LEF, GDS, Netlist, LIB, etc., and then … Read more
This project is a real project practical training, focusing on low-power UPF design. The backend parameters are as follows: Process: 12nm Frequency:2.5GHz Resources: 2000_0000 instances Flow: Partition Flow Partition Steps: Clock Structure Analysis: Reset Structure Analysis: Let’s compare the resources of A72 and A7. The number of A72 gates is 13 times that of A7! … Read more
Recording some commonly used IC termsSoftware Section:EDA Electronic Design Automation, a large number of EDA tools are required in the IC design processVCS Synopsys’s digital front-end simulation toolVerdi Synopsys’s digital front-end debug toolFSDBA commonly used waveform file format, opened withVerdiVCD Value Change Dump, a general waveform file format, detailed information but larger file sizeDC Design … Read more
The design of SOC’s SRAM, with waveform simulation verification using VCS + Verdi. SRAM serves as system cache, existing in the form of an AHB Slave. SRAM host features: supports 8-bit, 16-bit, and 32-bit read/write operations; single-cycle read/write; low power operation (the system can choose one or more SRAMs); supports DFT/BIST functionality.1. sramc_top is the … Read more
As the demand for battery life and energy efficiency in electronic devices continues to rise, low power design has become a critical aspect of chip design. The low power design strategies in DFT (Design For Testability) aim to reduce power consumption during both the testing phase and normal operation while ensuring chip test quality and … Read more
Original link:https://pubs.acs.org/doi/10.1021/jacs.4c14511 First authors:Yaling Jiang and Peimeng Qiu Corresponding authors:Peng Li and Shengli Chen Corresponding author affiliation:Wuhan University, China 【Core Innovation Point】 The authors systematically elucidate for the first time the impact of oxygen affinity (the affinity of metal surfaces for *OH) on the kinetics of the alkaline hydrogen evolution reaction (HER), which fundamentally arises … Read more
JTAG (Joint Test Action Group) is an international standard testing protocol (IEEE 1149.1) primarily used for testing, debugging, and programming chips, PCBs, and systems. Through a dedicated hardware interface and protocol, it provides non-intrusive access to the internal circuits of chips. The JTAG protocol is widely used in embedded development, hardware verification, and fault diagnosis. … Read more
In low power designs with multiple power domains, there are many interactive signals between different power domains. If one power domain is powered off, the signals output from that power domain to another power domain that is still powered on need to be isolated. The reason is that the signals from the powered-off power domain … Read more
Academic Paper Sharing The Atomic-Level Structure of Cementitious Calcium Aluminate Silicate Hydrate DOI：10.1021/jacs.0c02988 Summary / Abstract Despite the extensive use of aluminum-rich blended cements for over 30 years, the structural nature of aluminum in the primary hydration product, calcium aluminate silicate hydrate (C-A-S-H), remains unclear. Through first-principles calculations, we predict that aluminum will incorporate into … Read more
Question: JTAG has 5 ports, why is Trst an optional reset port? Question: If JTAG only retains 4 ports, how do we reset without Trst? Answer: The first question is simple; Trst can be replaced with Tms. What about the second question? Feel free to discuss in our knowledge community. Question: After adding mbist and … Read more