Understanding SDF 3.0 in Chip Post-Simulation (Part 1)
SDF files replace the delay information specified in STD/IO/Macro gate-level Verilog with the actual physical delay information extracted from QRC/Star-RC during VCS/NC-Verilog post-simulation runtime. Therefore, if the condition information in the SDF file is not present in the Verilog specify, it will raise a warning of SDFCOM_INF, meaning IO PATH not found. This article analyzes … Read more
