RTL Design

Detailed User Guide for Vivado 2018.3 Development Tool by Xilinx (AMD) – Creating Projects, Simulation, Board Programming, and Logic Analyzer Usage

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Detailed User Guide for Vivado 2018.3 Development Tool by Xilinx (AMD) - Creating Projects, Simulation, Board Programming, and Logic Analyzer Usage

User Guide for Vivado 2018.3 Software Copyright Beijing Zhixin Open Source Technology Co., Ltd. Document Update Record Date Updater Version Remarks 2024.03.10 xxx V0.1 First Draft V0.2 Review V1.0 Final Draft Hello everyone, welcome to Zhixin Technology’s FPGA boot camp, ready to embark on our great journey! As the saying goes, “Before the troops move, … Read more

Low Power Design Methods – Overview of Power Gating (Part 1)

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Low Power Design Methods - Overview of Power Gating (Part 1)

Leakage power consumption has increased with each generation of CMOS technology. This leakage power not only poses a serious challenge for battery-powered or portable products but is also becoming an issue that wired devices such as servers, routers, and set-top boxes must address. To reduce the total leakage power consumption of chips, it is best … Read more

Basic Development Process of FPGA and ASIC

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Basic Development Process of FPGA and ASIC

Title: Briefly describe the ASIC design process and list the tools used in each part. Basic ASIC Development Process Chip Architecture, considering chip definition, process, and packaging. RTL Design, described using Verilog, System Verilog, or VHDL. Functional Simulation, simulation under ideal conditions. Verification, using UVM verification methodology and FPGA prototype verification. Synthesis, logic synthesis, mapping … Read more

Why Caution is Required When Using For Loops in RTL Design

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Why Caution is Required When Using For Loops in RTL Design

I have been writing RTL for over a decade and have encountered various engineering coding standards, constraints, and suggestions. Therefore, I am summarizing my experiences at this stage. The Verilog/SV coding suggestions and some engineering requirements mentioned and discussed in this series are based on what I have encountered and understood during my work process. … Read more

A Simple Written Test Question on Low Power Design

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A Simple Written Test Question on Low Power Design

1. Concept Composition of Power Consumption: Three main sources of power consumption: surge, static power, and dynamic power; Surge Current: Refers to the maximum instantaneous input current generated when the device is powered on, known as the inrush current; The surge current is device-dependent; Surge power is not our primary concern, so it is only … Read more

Low Power Design Techniques: Data Gating and Operand Isolation

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Low Power Design Techniques: Data Gating and Operand Isolation

Low Power Design Techniques: Data Gating (Data Gating) and Operand Isolation (Operand Isolation) Previously, we discussed Clock Gating (Clock Gating), which is a well-known low power design technique. It can be easily applied during the logic synthesis stage without requiring changes to the RTL, making it one of the more straightforward methods for achieving low … Read more

Low Power Design in Digital Chips

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Low Power Design in Digital Chips

Power consumption is a critical performance metric in chips, sometimes even determining the success or failure of a chip. As is well known, the recent “Snapdragon Fire Dragon” incident significantly impacted the market share of this chip. For industrial-grade and automotive-grade chips, the impact of power consumption is not very apparent. However, for consumer-grade chips … Read more

How Engineers Can Excel in RTL Design

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How Engineers Can Excel in RTL Design

RTL is an essential part of IC system design. How important is RTL design? Essentially, the logical functions of IC systems are implemented in RTL, so many IC projects are closely tied to RTL design. Today, let’s discuss how to excel in RTL design. Generally, once the preparatory work and product requirements are determined, engineers … Read more

Introduction to Low-Power Design in Digital ICs (Part 5)

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Introduction to Low-Power Design in Digital ICs (Part 5)

Source: Content fromhttp://www.cnblogs.com/IClearner/ , Author: IC_learner, Thank you. This section mainly introduces the use of gated clocks for low-power design. (4) Gated Clock The gated clock was briefly described in my first blog; here I will provide a more detailed description. We will mainly learn what gated clock circuits are, when to use gated clocks, … Read more

Summary of Low Power Design in ASIC Design + Book Recommendations

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Summary of Low Power Design in ASIC Design + Book Recommendations

1. Low Power Design With the promotion of handheld portable devices, the issue of low power design has become increasingly important. Lower chip power consumption means longer usage time for portable devices, increased lifespan of chips due to reduced power consumption, better control of heat dissipation, and the ability to make devices smaller, among other … Read more