How to Build a Basic Testbench for SoC Projects Author:lshj98115 (Compiled from EETOPBBS ） The purpose of writing this document is to give everyone a clearer understanding of how to build a SoC project’s Testbench. You can follow this document step by step to set up a basic SoC project’s testbench. This document focuses on … Read more
The first thing to focus on when designing a chip is its PPA (Performance, Power, Area). This article discusses the second P, Power consumption, and how to achieve low power design in RTL, which is crucial for the battery life of mobile devices. Don’t let your chip unnecessarily increase power consumption. Data Path Register Sampling … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. When designing chips, the first thing to focus on is the chip’s PPA (Performance, Power, Area). This article discusses the second P, Power consumption, and how … Read more
Before making a decision, hesitation may be necessary. However, once a decision is made, one should move forward without looking back. ― ― Dazuo Ishikawa Unknowingly, I have written several articles on the topic of SoC power consumption, so let’s summarize them. SoC Design Power Consumption — Introduction SoC Design Power Consumption — Clock Gating … Read more
Recently, I have been reading “The Art of Hardware Architecture”, and this blog post is also derived from the content in the book. With the advancement of technology, low-power design has become increasingly important.As a digital front-end designer, let’s take a look at how to reduce power consumption at the RTL level. In large-scale ASIC … Read more
Here are the results from the past two days, implementing FPGA fixed-point decimal calculation in Verilog. There will be N parts, including addition, multiplication, division, square root, square, etc. Currently, addition and multiplication have been debugged, while division, square root, and square are not yet completed. Due to time constraints, this blog post will directly … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. Comprehensive Attributes In the Vivado Design Suite, the Vivado synthesis can synthesize various types of attributes. In most cases, these attributes have the same syntax and … Read more
In the design of complex systems such as 5G wireless, satellite communication, radar detection, and aerospace control, FPGA engineers play a crucial role. For an FPGA team, it is essential to complete the product design and verification according to project requirements, ensuring project delivery. To maintain efficient communication and progress among FPGA engineers in increasingly … Read more
The following question was asked by a VIP student from the Cortex-A72 training camp: After completing the single-core CPU PR, how do I output the data to TOP for multi-core hierarchy integration? Answer: After completing the single-core CPU, you need to output library files such as SDC, DEF, LEF, GDS, Netlist, LIB, etc., and then … Read more
This project is a real project practical training, focusing on low-power UPF design. The backend parameters are as follows: Process: 12nm Frequency:2.5GHz Resources: 2000_0000 instances Flow: Partition Flow Partition Steps: Clock Structure Analysis: Reset Structure Analysis: Let’s compare the resources of A72 and A7. The number of A72 gates is 13 times that of A7! … Read more