Digital Signal Processing Experiment Based on Matlab: Parseval’s Theorem, Time Domain Energy = Frequency Domain Energy, Unitary Matrix

Digital Signal Processing Experiment Based on Matlab: Parseval's Theorem, Time Domain Energy = Frequency Domain Energy, Unitary Matrix

The last experiment in class on October 13 was to prove this. I wasn’t very good at manual proofs, but a numerical simulation code solved it in no time. It has been inconvenient to write mathematical formulas on WeChat, so I delayed for more than a month before writing this article.The Fourier transform is often … Read more

Overcoming the Challenge of Meta-Methylation of Pyridine: A Cost-Effective Aldehyde-Catalyzed Strategy Brings New Breakthroughs

Overcoming the Challenge of Meta-Methylation of Pyridine: A Cost-Effective Aldehyde-Catalyzed Strategy Brings New Breakthroughs

Image source: J. Am. Chem. Soc.Introduction:The introduction of methyl groups can significantly enhance the activity of drugs, thus driving the development of various methylation strategies. Among these, C-H methylation is particularly noteworthy, but a universal method for meta-C-H methylation of pyridine—one of the most common nitrogen-containing heterocycles in pharmacophores—remains absent. This article reports a method … Read more

Is the Chip Ready for Tape-Out Once the Verilog Code is Completed?

Is the Chip Ready for Tape-Out Once the Verilog Code is Completed?

If you want to create a SoC chip, self-develop customized IPs to highlight differentiation, and purchase other general-purpose IPs, then connecting them is all that is needed. Making an SoC is just about connecting the dots. Once the Verilog code is done, can the chip be sent for tape-out? Let’s not even talk about the … Read more

Is the Chip Ready for Tape-Out Once the Verilog Code is Completed?

Is the Chip Ready for Tape-Out Once the Verilog Code is Completed?

If you want to create a SOC chip, self-develop customized IPs to highlight differentiation, while purchasing general-purpose IPs and simply connecting them, making a SOC is just about connecting the dots. Once the Verilog code is finished, is the chip ready for tape-out? Let’s not even discuss the technology of connecting the SOC; what happens … Read more

Is the Chip Ready for Tape-Out Once the Verilog Code is Completed?

Is the Chip Ready for Tape-Out Once the Verilog Code is Completed?

If you want to create a SOC chip, self-develop customized IP to highlight differentiation, and purchase other general-purpose IP, then just connect them together. Making a SOC is just about connecting the dots. Once the Verilog code is finished, is the chip ready for tape-out? Let’s not even talk about the technology of connecting the … Read more

Overview of SoC Reset Tree Design

Overview of SoC Reset Tree Design

1. Introduction The design of the reset tree for SoC (System on Chip) is a critical aspect that ensures the chip can reliably start and recover under various conditions. The reset tree, as a crucial yet often overlooked infrastructure within the SoC, is responsible for safely, reliably, and orderly transmitting reset signals generated externally or … Read more

How to Improve DFT Efficiency for SoC Chips?

How to Improve DFT Efficiency for SoC Chips?

Today, semiconductor companies face severe challenges related to shrinking technology nodes, expanding design scales, and broadening system scales (known as the “three major scaling challenges”). These challenges have a wide-ranging impact on design development, manufacturing, and functional operations, all of which affect the company’s operating profits. At the same time, the complexity of large System … Read more

Applications Of DFT Calculations In Dual-Atom Catalysts

Applications Of DFT Calculations In Dual-Atom Catalysts

Academic Exchange Website(www.xueyanhui.com) Register and member verification can receive up to 1100 yuan coupons Maximum discount for first order 200 yuan! Introduction: Dual-atom catalysts (DACs) have tunable electronic structures and spin states, which can enhance the performance of electrochemical reactions. By introducing a second metal, the electronic structure and spin state of the metal center … Read more

Debugging Process of 2.5GHz A72 Backend by a Frontend Engineer

Debugging Process of 2.5GHz A72 Backend by a Frontend Engineer

Documenting the debugging process of a frontend engineer involved in the 2.5GHz A72 backend: A fellow from the 2.5GHz A72 training camp asked: What are these PBUF_DATA? What is PBUF_CLK? Are all IO PORT BUF called this? Why should they be deleted? Answer: The IO buffer was added in the synthesis script, so the backend … Read more