Article Title: RISC-V Word Load Instruction Optimization Based on Linker All Authors: Wu Xinlong, Liao Chunyu First Affiliation: Institute of Software, Chinese Academy of Sciences Publication Date: 2022, 31(9): 24–30 Abstract Abstract RISC-V, as a representative of reduced instruction set computing, also reflects some of the drawbacks of reduced instruction sets, one of which is … Read more
Previously, we discussed how to run the RISC-V kernel on QEMU. Now, let’s talk about how to use Eclipse + GDB to debug the kernel on the QEMU platform. ${SIFIVE_DIR} is the local root directory of the freedom-u-sdk open-source project. 1. Configure BBL Configure the bootloader and generate debugging information. Enter the ${SIFIVE_DIR}/work/riscv-pk directory, which … Read more
Article Title: Cloud Task Scheduling System for RISC-V Heterogeneous Clusters Based on Kubernetes All Authors: Jiang Xiaobin, Xiong Yixiang, Zhang Heng, Hou Pengpeng, Wu Yanjun, Zhao Chen First Affiliation: Institute of Software, Chinese Academy of Sciences Publication Time: 2022, 31(9): 3–14 Abstract Summary With the widespread application and attention in the field of cloud computing, … Read more
Abstract: The RISC-V instruction set has formed a significant advantage over ARM and Intel due to its open-source sharing, and its application is gradually expanding globally, resulting in a large amount of research literature. This study uses important literature on RISC-V themes worldwide as a dataset and analyzes the research trends, main research institutions, and … Read more
RISC-V is also known as “the Linux of CPUs.” For some, this title feels like a legacy and an innovation at the same time, especially if you are a staunch believer in open source. However, I am a true pragmatist, and the excessive marketing of RISC-V has made me lose interest in the term. It … Read more
RISC-V is an instruction set architecture (ISA) for microprocessors, and people’s opinions about it are polarized. This is especially true given the apparent competition between the ARM and RISC-V camps. This makes sense. RISC-V and ARM represent fundamentally different philosophies on how to design RISC chips. RISC-V has a long-term view that emphasizes simplicity, avoiding … Read more
| Source: SIMIT Strategic Research Office (ID: SIMITSRO) Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences The two major architectures of current CPUs are CISC (Complex Instruction Set) and RISC (Reduced Instruction Set). x86 is the representative architecture of CISC, occupying over 95% of the desktop computer and server market. Arm, as … Read more
In the past year or two, the open-source instruction set architecture RISC-V has received unprecedented support from the industry due to its advantages such as open-source, free, modular, and scalable. Major companies including Qualcomm, Google, NVIDIA, Samsung, Western Digital, SiFive, PingTouGe, ChipLink, XuanYuan Microelectronics, GigaDevice, and hundreds of others are vigorously supporting the RISC-V ecosystem, … Read more
X-Silicon Inc. (XSi) has created a new RISC-V microprocessor architecture that combines RISC-V CPU cores with vector capabilities and GPU acceleration into a single chip. According to Jon Peddie Research, the CPU/GPU hybrid chip is open-source and is designed to handle a variety of functions typically managed by dedicated CPUs and GPUs, aiming to do … Read more
With the stagnation of Moore’s Law and system-level enterprises beginning to attempt to create their own chips, EDA and IP vendors seem to know that their spring has arrived—because their customer base has expanded. However, for EDA/IP vendors, there remains a massive obstacle in front of them: the complexity and high threshold of chip design … Read more