Summary of RISC-V Microarchitecture (1) – Introduction to Pipeline (Differences with ARM)
A brief block diagram of a certain RISC-V Level 1 The storage architecture of RISC-V (from inside to outside): 1)Reg 2)TCM (Tightly Coupled Memory, divided into I/D) / LM (Local Memory, divided into I/D) 3)TLB lookup (Translation Lookaside Buffer, a fast cache of recent address mappings) – TLB hit: avoids Page Table Lookup – TLB … Read more