(Source: Tomi Rantakari, CEO of ChipFlow, and Luca Testa, COO of Keysom)RISC-V has been a hot topic in the semiconductor industry for many years, and for good reason. As an open standard ISA alternative to traditional processor architectures like ARM and x86, it holds great promise, but its widespread adoption faces significant obstacles. Clearly, RISC-V … Read more
The MCU market has undergone significant changes in recent years due to various factors such as the pandemic, supply chain destocking, and technological advancements. With the rise of Chinese MCU manufacturers, global market competition has intensified, and technological innovation has accelerated, promising continuous growth in multiple fields in the future. What everyone wants to know … Read more
According to reports from Electronic Enthusiasts (by Zhou Kaiyang), for any major chip manufacturer, the choice of Instruction Set Architecture (ISA) is made with great caution. The ISA not only determines the ease of chip development but also dictates the software and development ecosystem tied to it, potentially impacting market competition. However, in this crucial … Read more
According to reports from Electronic Enthusiasts (by Zhou Kaiyang), data centers, as the most focused market for CPU, GPU, and accelerator manufacturers, naturally cannot miss the involvement of the new architecture RISC-V. In previous articles, we have introduced some progress of RISC-V in data centers. Although RISC-V has not shown significant momentum in general-purpose CPUs … Read more
If Matlab is banned, it does not mean that open-source Python and Julia can be used freely, and even the ancestral C language may not be safe. Just like the new Arm technology being banned for Huawei does not mean that Huawei can freely use the so-called open-source RISC-V. The leaders of open-source technology are … Read more
This article is one of the series in the “RISC-V CPU Design” column. Note: This article is excerpted from the first domestic book that systematically introduces CPU and RISC-V design, titled “Hands-on Guide to CPU Design: RISC-V Processor Edition” by “Silicon Farmer Alexander” (expected to be released in March-April 2018). The phrase “dynamic as a … Read more
The Power Game of Standard Setting Instruction Set Competition： RISC-V Vector Extension：The Andes AX45MPV core achieves INT8 matrix acceleration, outperforming the ARM Cortex-M55 by 40%, with licensing costs only 1/5. ARM Confidential Computing：Introduces Realm Management Extension (RME) to build hardware-isolated secure enclaves, fully adopted by Microsoft Azure Sphere. Middleware Undercover War： Apache TVM Unity：Supports direct … Read more
This year’s IIC Shanghai, while similar in arrangement to previous years with forums on power supply, MCU, EDA/IP, and the China IC Leaders Summit, has a notable difference: everyone is talking about AI. Almost all topics revolve around AI—even discussions related to power supply and testing are intertwined with AI. This is closely related to … Read more
Have you ever thought that the mobile phones, computers, and even bank servers you use every day might be exposed to hackers? Just last month, Samsung and a South Korean university tore away the last veil of ARM chip security—the so-called “absolute security” memory protection mechanism was pierced like paper in their hands. Even more … Read more
★ Welcome to the OERV Biweekly Report column, today marks the seventeenth issue. This column regularly introduces the work progress of the OERV team, community affairs, and related activity information, hoping to learn and progress together with everyone. Interested partners are welcome to leave messages for discussion in the public account backend! Overall Progress Version … Read more