Since the summer of 2010, the Berkeley research team has spent about four years designing and developing a complete new instruction set. This new instruction set is called RISC-V. From its official release in 2014, RISC-V has faced various doubts, but by 2017, the Indian government announced significant funding for RISC-V-based processor projects, making RISC-V … Read more
In the design of CPU cores, SIMD (Single Instruction Multiple Data) is a commonly used data parallel processing method that operates on multiple data elements simultaneously through a single instruction to enhance the computational efficiency and speed of the processor. SIMD has a wide range of applications, such as image processing, scientific computing, encryption and … Read more
May. Click the blue text to follow us 2025.05 In May 2010, Andrew Waterman, a student at the University of California, Berkeley, sent an email to his professors. After experimenting with various teaching methods for a three-month project, he concluded: They should revive the dying microprocessor architecture DEC Alpha. “I don’t see what new things … Read more
(Source: Semiconductor Industry Observer)In May 2010, Andrew Waterman, a student at the University of California, Berkeley, sent an email to his professors. After experimenting with various teaching methods for a three-month project, he concluded:They should revive the nearly extinct microprocessor architecture DEC Alpha.“I don’t see how we can create anything new,” Waterman said. “This has … Read more
(Source: csis)The RISC-V architecture is an open international standard that specifies the interface between computer software and hardware. It serves as a shared language, setting parameters for communication and interoperability. The open standard provides a pathway for industry participants to collaborate and develop technological solutions, helping to accelerate innovation and limit the abuse of intellectual … Read more
A brief block diagram of a certain RISC-V Level 1 The storage architecture of RISC-V (from inside to outside): 1)Reg 2)TCM (Tightly Coupled Memory, divided into I/D) / LM (Local Memory, divided into I/D) 3)TLB lookup (Translation Lookaside Buffer, a fast cache of recent address mappings) – TLB hit: avoids Page Table Lookup – TLB … Read more
01 — New Member of the K1/M1 Family: Jupiter NXJupiter NX is a system on module (SoM) launched by Shenzhen Milk-V Technology, featuring the SpacemiT K1/M1 octa-core 64-bit RISC-V processor, designed as an alternative to NVIDIA Jetson Nano/NX.This module is compatible with the 260-pin SO-DIMM interface of Jetson Nano/Xavier NX, allowing it to work with … Read more
20220723: Issue 4 Kernel Updates v4: Fix RISC-V’s arch-topology reporting The arm64 topology code is largely applicable to RISC-V as well, so it has been made generic along with the removal of MPIDR related code, which appears to be redundant since ‘3102bc0e6ac7 (“arm64: topology: Stop using MPIDR for topology information”)’ replaced the code that actually … Read more
On December 12, the Shanghai headquarters of the China Economic Information Agency officially released the “Insights into the Development of China’s Semiconductor IP Industry” at the 2025 Semiconductor IP Industry Seminar. The report indicates that the global semiconductor IP industry has entered a rapid development phase. Although the localization exploration of China’s semiconductor IP started … Read more
In media reports, ARM mini China is set to IPO in mainland China. Following this, online discussions have linked this event with the development of RISC-V by the Berkeley research team in the United States, which has attracted over 100 technology companies including IBM, NXP, Western Digital, NVIDIA, Qualcomm, Samsung, Google, and Huawei to join … Read more