JTAG (Joint Test Action Group) is an international standard testing protocol (IEEE 1149.1) primarily used for testing, debugging, and programming chips, PCBs, and systems. Through a dedicated hardware interface and protocol, it provides non-intrusive access to the internal circuits of chips. The JTAG protocol is widely used in embedded development, hardware verification, and fault diagnosis. … Read more
JTAG: The Core Interface for Chip Testability Design In the field of integrated circuit (IC) design, Design for Testability (DFT) is a key technology to ensure high reliability and yield in chip production. JTAG (Joint Test Action Group), as a standard test access interface, has become an important means for modern chips to implement DFT … Read more
Hello everyone, welcome to <span>LiXin Embedded</span>. Today, we will discuss JTAG boundary scan. This tool is essential for testing PCB interconnections and internal chip logic, defined in the IEEE 1149.1 standard. If you haven’t read the first two articles in this series, I recommend going back to catch up on the basics of JTAG debugging. … Read more
Research on Fault Injection and Detection Methods for Aero-Engine Electronic Controllers Based on Boundary Scan Wang Yao, Wen Tiedun, Chen Yaping, Zhang Tianhong Nanjing University of Aeronautics and Astronautics, School of Energy and Power Engineering Abstract: The aero-engine electronic controller is a complex circuit system designed around numerous large-scale integrated circuits. Traditional contact-based fault injection … Read more
FPGA (Field Programmable Gate Array) as a programmable logic device has been widely used in various digital system designs, and the JTAG interface is one of the most commonly used debugging/programming interfaces. Its quality directly affects the performance and reliability of the FPGA. Therefore, it is essential to diagnose and test the JTAG to prevent … Read more
Click the card below to follow Arm Technology Academy This article is authorized to be transferred from the WeChat public account “Electronic Circuit Development Learning”. This article mainly shares content related to JTAG boundary scan. How did I learn about boundary scan? This starts with my purchase of an FPGA board. Recently, I found an … Read more
This article mainly introduces the pin definitions, interface standards, boundary scan, and TAP controller of the JTAG bus. JTAG (Joint Test Action Group) is an international standard testing protocol (IEEE 1149.1 compatible), primarily used for internal chip testing. Most advanced devices now support the JTAG protocol, such as ARM, DSP, FPGA, etc. The standard JTAG … Read more
Hello everyone, I am Pi Zi Heng, a serious tech enthusiast. Today, I will talk about the interface standard JTAG in embedded debugging. In embedded development, it is inevitable to simulate and debug code, especially when the application logic becomes complex to a certain extent. It is common to introduce some logical bugs while writing … Read more
This article mainly introduces the terms related to JTAG that are easily confused: JTAG JTAG (Joint Test Action Group): In the early application of chips, different manufacturers had different testing methods for chips, making the joint testing of chips and boards very difficult. A unified testing method was needed to solve this problem. The JTAG … Read more
1. What is a BSDL File? In the last article, we introduced the basics of JTAG boundary scan, today we will look at a file that is essential for boundary scan testing, the BSDL file. BSDL, Boundary Scan Description Language is an abbreviation for Boundary Scan Description Language, a subset of VHDL that conforms to … Read more