FPGA (Field Programmable Gate Array) as a programmable logic device has been widely used in various digital system designs, and the JTAG interface is one of the most commonly used debugging/programming interfaces. Its quality directly affects the performance and reliability of the FPGA. Therefore, it is essential to diagnose and test the JTAG to prevent … Read more
Click the card below to follow Arm Technology Academy This article is authorized to be transferred from the WeChat public account “Electronic Circuit Development Learning”. This article mainly shares content related to JTAG boundary scan. How did I learn about boundary scan? This starts with my purchase of an FPGA board. Recently, I found an … Read more
This article mainly introduces the pin definitions, interface standards, boundary scan, and TAP controller of the JTAG bus. JTAG (Joint Test Action Group) is an international standard testing protocol (IEEE 1149.1 compatible), primarily used for internal chip testing. Most advanced devices now support the JTAG protocol, such as ARM, DSP, FPGA, etc. The standard JTAG … Read more
Hello everyone, I am Pi Zi Heng, a serious tech enthusiast. Today, I will talk about the interface standard JTAG in embedded debugging. In embedded development, it is inevitable to simulate and debug code, especially when the application logic becomes complex to a certain extent. It is common to introduce some logical bugs while writing … Read more
This article mainly introduces the terms related to JTAG that are easily confused: JTAG JTAG (Joint Test Action Group): In the early application of chips, different manufacturers had different testing methods for chips, making the joint testing of chips and boards very difficult. A unified testing method was needed to solve this problem. The JTAG … Read more
1. What is a BSDL File? In the last article, we introduced the basics of JTAG boundary scan, today we will look at a file that is essential for boundary scan testing, the BSDL file. BSDL, Boundary Scan Description Language is an abbreviation for Boundary Scan Description Language, a subset of VHDL that conforms to … Read more
Following the previous article, we learned about the erase, write, and read functions of FLASH, but there is still a lack of understanding regarding the relationship with JTAG. This article supplements the JTAG part. First, let’s take a look at the hierarchical structure of JTAG programming FLASH, as shown in the figure below: The physical … Read more
Boundary Scan Technology can not only test the logical functions of chips or PCBs but also check for faults in the connections between IC (Integrated Circuit) and PCB (Printed Circuit Board). Therefore, it has become mainstream in the design for testability of digital systems. The IEEE established the relevant standard, IEEE 1149.1, in 1990, which … Read more
Previous article, introduced the JTAG boundary scan application based on STM32F103, demonstrated the application of TopJTAG Probe software, and the basic functions of boundary scan. This article introduces the boundary scan application based on Xilinx FPGA, which is almost the same. 1. Obtain the Chip’s BSDL File The method of obtaining the BSDL file for … Read more
Basic structure of JTAG: Standard Ports: TCK (Test Clock) – This signal synchronizes the operation of the internal state machine. TMS (Test Mode Select) – This signal samples at the rising edge of TCK to determine the next state. TDI (Test Data Input) – This signal represents the data for the device under test or … Read more