If you want to create a SoC chip, self-develop customized IPs to highlight differentiation, and purchase other general-purpose IPs, then connecting them is all that is needed. Making an SoC is just about connecting the dots. Once the Verilog code is done, can the chip be sent for tape-out? Let’s not even talk about the … Read more
If you want to create a SOC chip, self-develop customized IPs to highlight differentiation, while purchasing general-purpose IPs and simply connecting them, making a SOC is just about connecting the dots. Once the Verilog code is finished, is the chip ready for tape-out? Let’s not even discuss the technology of connecting the SOC; what happens … Read more
If you want to create a SOC chip, self-develop customized IP to highlight differentiation, and purchase other general-purpose IP, then just connect them together. Making a SOC is just about connecting the dots. Once the Verilog code is finished, is the chip ready for tape-out? Let’s not even talk about the technology of connecting the … Read more
Click the blue text to follow us “IEEE 1801, better known in the industry as the UPF standard, is a methodology for describing power intent, designing, and verifying power management architectures. Since its introduction, this standard has undergone four major updates, and compatibility issues between different versions have made it one of the hardest standards … Read more
To better serve everyone, I would like to report on my main business here. For design outsourcing, friends with backend outsourcing needs are welcome to contact me (WeChat ID: ic-backend2018), of course, if you have resources, you can also introduce them to me, and there will definitely be generous cash rewards (15% commission). PS: The … Read more
Documenting the debugging process of a frontend engineer involved in the 2.5GHz A72 backend: A fellow from the 2.5GHz A72 training camp asked: What are these PBUF_DATA? What is PBUF_CLK? Are all IO PORT BUF called this? Why should they be deleted? Answer: The IO buffer was added in the synthesis script, so the backend … Read more
“ 12nm process, 2.5GHz frequency, practical training on Cortex-A72 processor backend” 01 — Cortex-A72 Processor—Digital Backend Practical Training This project is a real project practical training, focusing on low-power UPF design, with backend parameters as follows: Process: 12nm Frequency:2.5GHz Resources:2000_0000 instances Flow:Partition Flow Partition Steps:: Clock Structure Analysis: Repetition Structure Analysis: Let’s compare the resources … Read more
This project is a real project practical training, focusing on low-power UPF design. The backend parameters are as follows: Process: 12nm Frequency:2.5GHz Resources: 2000_0000 instances Flow: Partition Flow Partition Steps: Clock Structure Analysis: Reset Structure Analysis: Let’s compare the resources of A72 and A7. The number of A72 gates is 13 times that of A7! … Read more
Isolation Units The SALT project utilized several different isolation techniques. The initial version of SALT was completed before tools supported the automatic insertion of isolation units. Therefore, we manually inserted these cells in the RTL. The interface between the CPU and the cache is particularly critical for timing and requires careful design and timing analysis. … Read more
In low power designs with multiple power domains, there are many interactive signals between different power domains. If one power domain is powered off, the signals output from that power domain to another power domain that is still powered on need to be isolated. The reason is that the signals from the powered-off power domain … Read more