The design of the power grid has a direct impact on chip performance and reliability. It is essential to ensure that the power grid provides sufficient power voltage to all transistors within the cells, allowing the chip to operate normally under all possible conditions within a certain noise tolerance. However, as technology shrinks, the threshold … Read more
Literature from IMEC, published in 2022, focuses on the impact of BSPDN on PPAT.The front end (FEOL) is an active driver of chip power/performance/area (PPA). As scaling approaches the physical limits of semiconductor devices, the back end (BEOL)/middle end (MEOL)/packaging becomes increasingly important for PPA improvements in chips/systems. At 2nm and below, BSPDN back interconnects … Read more
This literature is from IMEC, published in 2022, focusing on the impact of BSPDN on the study of PPAT.The front end (FEOL) is an active driver of chip power/performance/area (PPA). As scaling approaches the physical limits of semiconductor devices, the back end (BEOL)/middle end (MEOL)/packaging becomes increasingly important for PPA improvements in chips/systems. At 2nm … Read more
—Knowing and doing are the farthest distances in the world. In previous articles, we introduced the aspects that need to be considered in the front-end architecture and design of SoC, and provided some reference solutions. The last article described the relevant content of UPF, completing the overall plan and UPF. The next step is the … Read more