Recording some commonly used IC termsSoftware Section:EDA Electronic Design Automation, a large number of EDA tools are required in the IC design processVCS Synopsys’s digital front-end simulation toolVerdi Synopsys’s digital front-end debug toolFSDBA commonly used waveform file format, opened withVerdiVCD Value Change Dump, a general waveform file format, detailed information but larger file sizeDC Design Compiler, Synopsys’s digital synthesis toolICC IC Compiler, a software from Synopsys for automatic layout and routing, widely used by many companiesINNOVUS Cadence’s digital layout implementation tool,GDSII Layout file formatPT Prime Time, Synopsys’s static timing analysis toolVivado Vivado, an integrated design environment released by Xilinx in 2012 for FPGANCSIM Cadence’s digital front-end simulation toolModelsim Mentor’s digital front-end simulation tool, also known as QUESTASIMTessent Mentor’s DFT tool, with a high market share 
Language Section:Shell A commonly used scripting language, closely integrated with LinuxPython A popular scripting language, widely used in artificial intelligencePerl A commonly used scripting language, very suitable for text processingTCL Tool Command Language, a scripting language for scheduling various softwareVerilog Hardware Description LanguageSystemVerilog Chip verification language 
Protocol Section:APB Advanced Peripheral Bus, one of the AMBA bus specifications launched by ARM, mainly used for connecting low-bandwidth peripheralsAHB Advanced High-Performance Bus, one of the AMBA bus specifications launched by ARM, mainly used for connecting high-performance modulesAXI Advanced eXtensible Interface, one of the AMBA bus specifications launched by ARM, designed for high-performance, high-bandwidth, low-latency on-chip busesGPIO General Purpose Input Output, bus expanderHDMI High Definition Multimedia Interface, a digital video/audio interface technology specificationSPI Serial Peripheral Interface, a high-speed, full-duplex, synchronous communication busI2C Inter-Integrated Circuit, a commonly used multi-directional control bus with only two wiresUART Universal Asynchronous Receiver/Transmitter, a common IP moduleCAN Controller Area Network, an ISO international standard serial communication protocolMIPI Mobile Industry Processor Interface, an open standard and specification for mobile application processorsOCP Open Core Protocol, an efficient, bus-independent, configurable, and highly scalable interface protocolPCIe Peripheral Component Interconnect Express, a common bus standardUSB Universal Serial Bus, a high-speed bus protocol for connecting peripherals 
Chip Section:IC Integrated CircuitLSI Large-scale Integrated CircuitVLSI Very-large-scale integrationASIC Application Specific Integrated Circuit, the mainstream design process for chip design companiesFPGA Field Programmable Gate Array, corresponding to the ASIC processSoC System on Chip, generally refers to larger chips, mostly containing CPU/MCU, etc.MCU Microcontroller Unit, the main control moduleDSP Digital Signal Processing module, commonly used in algorithm implementation by IC design companiesCPLD Complex Programmable Logic Device, similar to FPGAIP Intellectual PropertyFE Front End, the front-end design process in IC designDV Design Verification, the verification process in IC designBE Back End, the back-end design process in IC designFULLCHIP Fullchip level, commonly used in digital front-end design and verification, refers to system-level and chip-levelGLS Gate-level simulation, refers to gate-level simulation in digital verificationLPS Low power simulation, commonly used in low-power design verificationFM Formal verification, comparing netlists with VerilogSTA Static Timing Analysis, an important step in the digital IC design processNetlist Gate-level netlist, generally the netlist file generated by RTL Code after synthesisECO Engineering Change Order, modifications to chip design can only be made at the gate level in the later stages of the projectDFT Design for Test, a design method adopted to enhance chip testability, an important step in the digital IC processATPG Auto Test Pattern Generator, a common process in DFT for automatic generation of test vectorsBIST Built-in Self-Test, a common process in DFTJTAG Joint Test Action Group, an international standard testing protocol, commonly used for chip testingCTS Clock Tree Synthesis, an important process in digital back-end implementationPD Physical Design, generally refers to layout design in digital back-endPV Physical Verification, verification needed after digital layout implementationAPR Auto Place and Route, the main process of digital back-end layout implementationNDR Non-Default Route, an important concept in layout implementationLayout Layout, refers to the final layout generated for the chip, similar to design blueprints in the construction industryERC Electronic Rule Check, checks whether the layout complies with electrical rules after IC designLVS Layout versus Schematic, checks the consistency between the layout and the circuit diagram after layout generationDRC Design Rule Check, checks whether the generated layout complies with the design rules provided by the foundry, such as width, spacing, area, etc.signoff Acceptance mechanism, acceptance criteriaTapout Tape-out, sending the final layout file to the foundry for productionDAC Digital to Analog Converter, a circuit for converting digital signals to analog signalsADC Analog to Digital Converter, a circuit for converting analog signals to digital signalsCAD Computer-Aided Design, software automation assistanceCDC Clock Domain Crossing, asynchronous clock timing check, an important step in digital designDMA Direct Memory AccessRAM Random Access MemoryROM Read Only Memory, non-volatile memoryEEPROM Electrically Erasable Programmable Read-Only MemoryDRAM Dynamic Random Access Memory, the most common system memorySRAM Static Random Access MemoryFLASH Flash EEPROM Memory, combines the fast data reading characteristics of RAMLUT Look Up Table, used to store some data, essentially a RAMIEEE Institute of Electrical and Electronics EngineersSPEC Specification, product specifications that every engineer must writeRTL Register Transfer Level, often refers to the level described using VerilogDUT Design Under Test, the design module to be testedDUV Design Under Verification, similar to DUTTestbench Testing platform, a platform used for digital verification testingUVM Universal Verification Methodology, a mainstream digital verification methodology based on SystemVerilogREGRESSION Regression testing, simply put, running all test cases repeatedly until there are no errors for a stable periodCOVERAGE Coverage, a commonly used term in digital verification, mainly includes code coverage and functional coverage