Source: Semika Original Author: Semika This article provides a detailed introduction to chip testing. Chip testing can be broadly divided into two main parts: CP (Chip Probing) and FT (Final Test). Some chips also undergo SLT (System Level Test). Additionally, some specific chips require reliability testing. CP Testing CP (Chip Probing) testing, also known as … Read more
The design of SOC’s SRAM, with waveform simulation verification using VCS + Verdi. SRAM serves as system cache, existing in the form of an AHB Slave. SRAM host features: supports 8-bit, 16-bit, and 32-bit read/write operations; single-cycle read/write; low power operation (the system can choose one or more SRAMs); supports DFT/BIST functionality.1. sramc_top is the … Read more
DAP and JTAG There are various ways to connect to the Debug Access Port (DAP), which differ in cost, invasiveness, and security. The DAP allows access to the core within the chip, which is typically the first to boot or is a dedicated microprocessor used for managing chip boot, debugging, and initializing DVFS and DRAM … Read more
JTAG (Joint Test Action Group) is an international standard testing protocol (IEEE 1149.1) primarily used for testing, debugging, and programming chips, PCBs, and systems. Through a dedicated hardware interface and protocol, it provides non-intrusive access to the internal circuits of chips. The JTAG protocol is widely used in embedded development, hardware verification, and fault diagnosis. … Read more
In the complex journey of chip development, Post-Silicon Validation (PSV) plays a crucial role. Once the chip transitions from design blueprints to actual silicon wafers, PSV becomes the core process to verify whether it meets the expected functionality and performance. From a technical perspective, PSV primarily involves inputting various test vectors into the chip to … Read more