Insights on AHB Bus Learning The AMBA 3 AHB-Lite protocol is designed for high-performance synthesizable designs, supporting a single bus master and providing high bandwidth operations. It features burst transfers, single clock edge operations, non-tristate implementations, and configurable data bus widths from 64 bits to 1024 bits, making it suitable for connecting internal storage devices, … Read more
Hello everyone, I am Pi Zi Heng, a serious technical person. Today, I will introduce to you the actual capture of Flash signal waveforms to observe the AHB read access situation under the i.MXRT FlexSPI peripheral. In the previous article “Actual Capture of Flash Signal Waveforms to Observe AHB Read Access under i.MXRT FlexSPI Peripheral … Read more
Today, Pi Zi Heng introduces the actual capture of Flash signal waveforms to examine the AHB read access conditions under the FlexSPI peripheral of i.MXRT. In the previous article “Actual Capture of Flash Signal Waveforms to Examine AHB Read Access Conditions Under the FlexSPI Peripheral of i.MXRT (With Prefetch)” Pi Zi Heng captured the timing … Read more
The design of SOC’s SRAM, with waveform simulation verification using VCS + Verdi. SRAM serves as system cache, existing in the form of an AHB Slave. SRAM host features: supports 8-bit, 16-bit, and 32-bit read/write operations; single-cycle read/write; low power operation (the system can choose one or more SRAMs); supports DFT/BIST functionality.1. sramc_top is the … Read more
Introduction In the field of high-efficiency power conversion, the Asymmetric Half-Bridge (AHB) topology has become a core design solution for high-density power modules, electric vehicle chargers, and industrial power systems due to its simple structure, low switching losses, and soft-switching characteristics. As the “brain” of the AHB architecture, the AHB controller chip achieves efficient driving … Read more
Hello everyone, I am Pi Zi Heng, a serious technical person. Today, I will introduce how to modify the FlexSPI driver on i.MXRT to write NOR Flash using AHB. Recently, I wrote an article titled “The Two Key Characteristics of Serial NAND Flash Preventing XiP under i.MXRT FlexSPI”, where I discussed the Page Read waiting … Read more
1. Overview of Buses The computer system is centered around the microprocessor, and all devices must connect to the microprocessor and work in coordination. Therefore, the concept of a bus is introduced in the microprocessor, where all devices share the bus, and at any given time, only one device can send data (multiple devices can … Read more
This article is reprinted from the Jishu Community Jishu Column: Agile MM32 MCU Table of Contents Bus Architecture of MM32F5270 Case Study: Audio Player with Display Summary & Next The previous article introduced the MM32F5 series which utilizes the “Star” STAR-MC1 processor. If readers recall, the “Star” processor has a significant advantage over the M3 … Read more
First, it should be understood what a bus is. According to Baidu’s complete definition: a bus is a common communication line for transmitting information between various functional components of a computer, composed of wire transmission lines, classified according to the types of information transmitted by the computer. In fact, a bus is an internal structure … Read more
1. Introduction In the Linux device driver model, a bus is an abstract concept, a special type of device. In the implementation of the device model, the kernel specifies that each device in the system must be connected to a bus, which can be an internal Bus, a virtual Bus, or a Platform bus. The … Read more