First, let’s clarify what is meant by “timing” here, which refers to the logical relationships of a set of signals, rather than timing parameters like steptime and holdtime. If you want to understand why this article exists, please refer to the series “Where is FPGA Going” and “What HLS Does FPGA Need”. Here, we focus … Read more
The first thing to focus on when designing a chip is its PPA (Performance, Power, Area). This article discusses the second P, Power consumption, and how to achieve low power design in RTL, which is crucial for the battery life of mobile devices. Don’t let your chip unnecessarily increase power consumption. Data Path Register Sampling … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. When designing chips, the first thing to focus on is the chip’s PPA (Performance, Power, Area). This article discusses the second P, Power consumption, and how … Read more
There are many methods for low power design, but the most mature ones currently are gated power supply, multi-threshold voltage, and clock gating. Gated power supply technology involves adding a PMOS transistor between the pull-up network made of PMOS and VDD in some static CMOS circuits, or adding an NMOS transistor between the pull-down network … Read more
To make a simple 16-bit CPU, we first need to clarify what a CPU does. We should understand the composition of a computer (or its alternatives, since not only computers have CPUs; modern electronics are advanced, and many devices such as mobile phones, washing machines, televisions, and even your car are equipped with a CPU). … Read more
Here are the results from the past two days, implementing FPGA fixed-point decimal calculation in Verilog. There will be N parts, including addition, multiplication, division, square root, square, etc. Currently, addition and multiplication have been debugged, while division, square root, and square are not yet completed. Due to time constraints, this blog post will directly … Read more
Although the AXI interface is frequently used, many may not be aware that Vivado also integrates AXI Verification IP, which can serve as an AXI master, pass-through, and slave. In this content, we will explore how to use the AXI VIP as a master. Create a new Vivado project and a new block design named: … Read more
IntroductionThe author has previously been learning communication algorithms through MATLAB simulations and has recently started to learn how to implement the communication systems constructed in MATLAB simulations using FPGA. Due to the significant differences between MATLAB simulation code and Verilog code, and the unfamiliarity with FPGA implementations of communication systems, the author decided to write … Read more
1. MOSFET Driven Load 1.1 Definition A MOSFET driven load refers to a load that can be driven by components with switching functions such as switches, MOSFETs, or transistors. Common types include: (1) Resistive Load: Devices that generate heat through a resistive wire. (2) Inductive Load: Such as electromagnetic coils, solenoids, relays, solenoid valves, and … Read more
After completing the programming related to FPGA design, we need to write a tb file for functional verification. Here is a framework: ‘timescale 1ns/1ps module tb_module_name(); /* Input signals of the test module: signal types are defined as reg, ensure bit width consistency, ending with a semicolon */ /* Output signals of the test module: … Read more