Methods Related to Low Power: 1. Clock Gating The RTL code must follow the low power style, and there should be at least three or four registers after the enable signal for the tool to synthesize it into a clock gate. 2. Lower VT 3. Gate Level Power Optimization 4. In terms of architecture, this … Read more
1 SoC Concept System on Chip vs. System on PCB: The essence is to evolve the process technology to transform a module into an internal module. SoC aims for high integration and miniaturization within a single chip. SoC serves as the core, and it is certainly expanded and connected through PCB. System on PCB seeks … Read more
1 SoC Concept System on Chip vs. System on PCB: The essence is to evolve the process technology to transform a traditional module into an internal module. SoC aims for high integration and miniaturization within a single chip. SoC serves as the core, and it is certainly expanded and connected through PCB. System on PCB … Read more
The first thing to focus on when designing a chip is its PPA (Performance, Power, Area). This article discusses the second P, Power consumption, and how to achieve low power design in RTL, which is crucial for the battery life of mobile devices. Don’t let your chip unnecessarily increase power consumption. Data Path Register Sampling … Read more
There are many methods for low power design, but the most mature ones currently are gated power supply, multi-threshold voltage, and clock gating. Gated power supply technology involves adding a PMOS transistor between the pull-up network made of PMOS and VDD in some static CMOS circuits, or adding an NMOS transistor between the pull-down network … Read more
To effectively reduce power consumption, design engineers need to approach from multiple levels, including architecture design, circuit optimization, process selection, and more. This article will focus on circuit-level low-power design, introducing several common optimization methods, such as Clock Gating, Toggle Rate Optimization, Area Optimization, and Memory Low Power Management, to help engineers more efficiently reduce … Read more
Low Power Design in Video Codec This paper introduces three techniques: two-layer clock gating, skip mode, and a three-layer memory structure with a memory access unit, to optimize gate-level circuits and reduce power consumption in digital systems. Two-layer Clock Gating **Figure 1: Two Types of Clock Gating** Among the various power optimization techniques proposed, clock … Read more
With the increase in device density and clock frequency of chips under advanced processes, power consumption has also significantly increased. At the same time, the supply voltage and transistor threshold voltage have been reduced, leading to significant leakage current. High power consumption can cause excessive temperature during device operation, reducing reliability due to electromigration and … Read more
There are many power reduction methods that have been in use for some time, and these are mature technologies. This chapter describes some methods for low power design. Clock Gating A significant portion of the dynamic power consumption in a chip is wasted in clock balancing. More than 50% of dynamic power can be wasted … Read more
Today, I plan to start a new series on low power design. Although my experience in low power design is not extensive, I have worked on projects with high demands for low power consumption, so I have a general understanding of the common practices and main techniques in low power design. Additionally, due to various … Read more