From C Language to VHDL: Bridging the Gap Between Software and Hardware Thinking

From C Language to VHDL: Bridging the Gap Between Software and Hardware Thinking

Today, we will discuss the hardware design knowledge that every software programmer needs to understand, especially for those who are just starting to engage in hardware design. For developers who are already familiar with programming languages like C or Java, they often encounter misunderstandings when learning hardware description languages such as VHDL or Verilog. This … Read more

Is the Chip Ready for Tape-Out Once the Verilog Code is Completed?

Is the Chip Ready for Tape-Out Once the Verilog Code is Completed?

If you want to create a SOC chip, self-develop customized IP to highlight differentiation, and purchase other general-purpose IP, then just connect them together. Making a SOC is just about connecting the dots. Once the Verilog code is finished, is the chip ready for tape-out? Let’s not even talk about the technology of connecting the … Read more

Xilinx Common IP Core Series | Design and Implementation of a Signal Generator Based on DDS

Xilinx Common IP Core Series | Design and Implementation of a Signal Generator Based on DDS

「Xilinx Common IP Core Series」 Design and Implementation of a Signal Generator Based on DDS (Includes Verilog Code + Simulation Waveform) In fields such as communications, radar, and test instruments, the signal generator is one of the most fundamental and important modules. Whether for system validation or algorithm experimentation, a stable and flexible waveform source … Read more

UART Asynchronous Serial Communication Circuit Design Verilog Code for Quartus FPGA_C4_V2.1 Experimental Board

UART Asynchronous Serial Communication Circuit Design Verilog Code for Quartus FPGA_C4_V2.1 Experimental Board

Name: UART Asynchronous Serial Communication Circuit Design Verilog Code for Quartus FPGA_C4_V2.1 Experimental Board Software: Quartus Language: Verilog Code Function: Function Description Enhance the transmission rate of UART communication, supporting higher baud rates (such as 115200, 230400, or higher). Implementation Method 1. Optimize Baud Rate Division Use a higher system clock frequency (e.g., 100MHz) and … Read more

FPGA Functional Module: Photointerrupter Signal Reading

FPGA Functional Module: Photointerrupter Signal Reading

1. Photointerrupter 1.1 Common Types of Photointerrupters (1) Slotted Photointerrupter This sensor has the emitter and detector positioned opposite each other, detecting objects that pass through the slot between the emitter and detector. There are various photoelectric sensors with different slot widths or depths depending on the detected object. (2) Reflective Photointerrupter This type of … Read more

How is the Netlist of an FPGA Generated?

How is the Netlist of an FPGA Generated?

Have you ever encountered a situation where you want to share your code with someone else, but you only want them to use it without having access to the source code? In this case, you can provide them with the netlist file of your code.In this way, they will have usage rights but no modification … Read more

LCD1602 Module Driver Code Design in Verilog for Quartus Development Board

LCD1602 Module Driver Code Design in Verilog for Quartus Development Board

Name: LCD1602 Module Driver Code Design in Verilog for Quartus Development Board Software: Quartus Language: Verilog Code Function: Design of the LCD1602 module driver code 1. Using Quartus software 2. Using Verilog language 3. Input two sets of 16-bit binary data, allowing the LCD1602 to display the string “consume” along with the first group of … Read more

UART Serial Transmission and Reception String Design Verilog Code Quartus Simulation

UART Serial Transmission and Reception String Design Verilog Code Quartus Simulation

Name: UART Serial Transmission and Reception String Design Verilog Code Quartus Simulation Software: Quartus Language: Verilog Code Function: UART serial transmission and reception of strings Simulated transmission string “from my RISC-V SoC UART !!!!!!” 1. Project Files Edit 2. Program Files Edit 3. Testbench Edit 4. Simulation Diagram Edit Partial Code Display: `timescale 1ns / … Read more

FPGA-Based Electronic Quiz Buzzer Design Verilog Code Quartus Simulation

FPGA-Based Electronic Quiz Buzzer Design Verilog Code Quartus Simulation

Name: FPGA-Based Electronic Quiz Buzzer Design Verilog Code Quartus Simulation Software: Quartus Language: Verilog Code Function: FPGA-Based Electronic Quiz Buzzer This design is an FPGA-based four-channel intelligent quiz buzzer, featuring system reset, a 30-second countdown, and digital tube display functions. The buzzer is implemented through four main modules: debouncing, control, score management, and display control, … Read more

Recommended Books on FPGA/Verilog/System Verilog, Communication/OFDM/Wireless, and MATLAB

Recommended Books on FPGA/Verilog/System Verilog, Communication/OFDM/Wireless, and MATLAB

Recommended Book Series for Beginners in Communication 1: Principles of Communication and Study Guide for Communication Principles Recommended Book Series for Beginners in Communication 2: Detailed Explanation of MATLAB/Simulink Communication System Modeling and Simulation Recommended Book Series for Beginners in Communication 3: Oppenheimer’s Signals and Systems, Second Edition Recommended Book Series for Beginners in Communication … Read more