Recently, many people in the group have encountered the above situation, which has been quite puzzling. I had never faced such a situation before. If it were a common issue, there would surely be feedback on the official website. If it is a very specific case, then it can only be treated as a bug. … Read more
Clock constraint commands in Vivado create_clock create_clock -name <name> -period <period> -waveform {<rise_name> <fall_name> } {get_ports <input_port>} create_clock is used to create the primary clock create_clock -name <clk0> -period <10.000> -waveform {0 5} {get_ports clk0} (default state) create_clock -name <clk1> -period <10.000> -waveform {2 8} {get_ports clk1} create_generated_clock create_generated_clock is used to constrain derived clocks … Read more
Click the blue text above to follow us 01 Basic Overview Acceleration Card Model: Inspur YPCB_00338_1P1 FPGA Chip Model: XC7K480TFFG1156-2 FLASH Chip Model: MT28GU512AAA1EGC-0SIT VIVADO Version: Vivado 2019.2 02 Program Burning In formal engineering projects, after generating the bitstream and verifying the solution, users will burn the official version of the program into FLASH. This … Read more
Introduction In the FPGA development process, programming the bitstream file and using ILA for debugging are common operations. However, if the FPGA board is located in a server room or connected to a server via PCIe, we often have to run to the server room or next to the server with a laptop to connect … Read more
User Guide for Vivado 2018.3 Software Copyright Beijing Zhixin Open Source Technology Co., Ltd. Document Update Record Date Updater Version Remarks 2024.03.10 xxx V0.1 First Draft V0.2 Review V1.0 Final Draft Hello everyone, welcome to Zhixin Technology’s FPGA boot camp, ready to embark on our great journey! As the saying goes, “Before the troops move, … Read more
The Artix 7 series FPGA provides many DSP hardware units that can be configured for floating-point operations.In the Vivado IP configuration interface, the clock cycle for the module can be selected, and data can be read out after a specified number of clock cycles.The Floating Point IP resource user manual from Vivado.However, it is somewhat … Read more
This series of instructional videos is led by Xilinx Senior Strategic Applications Engineers, guiding you from the ground up to master HLS and UltraFAST design methodologies, helping you become an expert in system design and algorithm acceleration! Course Update Schedule:Every second and fourth Tuesday of the month Mechanism of HLSLesson 2 As the saying goes, … Read more
Problem Description After downloading the elf file, a message box pops up as shown in Figure 1, indicating that there is a problem with the software operation. However, the software runs correctly; for instance, the VGA interface displays images normally, as shown in Figure 2. Moreover, this error does not appear in Debug mode. Figure … Read more
Win a Backpack How Difficult Is It? Give it a Try! →_→ Long Press to Recognize Copyright Statement: This article was published by the blogger“cuter”.Reprinting is welcome, but the content of the blog must not be altered, nor used for any profit purposes. When reprinting, the author’s profile and copyright statement must not be deleted. … Read more
Previously, it was explained that when external registers need to be added, the bus interconnection module must be changed. In the bus interconnection module, each register has a wire connected to the bus interconnection module for reading data and enabling signals. If there are relatively few registers, it seems there is no problem. But what … Read more