Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the largest and best FPGA engineering community in China. With the continuous development of FPGAs, the number of built-in PCIE hard cores is increasing. This article introduces how to allocate the corresponding hardware pins using ZU11EG … Read more
Although the AXI interface is frequently used, many may not be aware that Vivado also integrates AXI Verification IP, which can serve as an AXI master, pass-through, and slave. In this content, we will explore how to use the AXI VIP as a master. Create a new Vivado project and a new block design named: … Read more
[HLS Video Tutorial 1] How Should Software Engineers Understand FPGA Architecture? [HLS Video Tutorial 2] HLS Working Mechanism [HLS Video Tutorial 3] Introduction to Vivado HLS Design Process
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. Comprehensive Attributes In the Vivado Design Suite, the Vivado synthesis can synthesize various types of attributes. In most cases, these attributes have the same syntax and … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. First, go to the official website to download the installation package: https://www.xilinx.com/support/download.html. Download the largest installation package that supports all OS like Windows/Linux. After downloading, proceed … Read more
In the design of complex systems such as 5G wireless, satellite communication, radar detection, and aerospace control, FPGA engineers play a crucial role. For an FPGA team, it is essential to complete the product design and verification according to project requirements, ensuring project delivery. To maintain efficient communication and progress among FPGA engineers in increasingly … Read more
Recently, many people in the group have encountered the above situation, which has been quite puzzling. I had never faced such a situation before. If it were a common issue, there would surely be feedback on the official website. If it is a very specific case, then it can only be treated as a bug. … Read more
Clock constraint commands in Vivado create_clock create_clock -name <name> -period <period> -waveform {<rise_name> <fall_name> } {get_ports <input_port>} create_clock is used to create the primary clock create_clock -name <clk0> -period <10.000> -waveform {0 5} {get_ports clk0} (default state) create_clock -name <clk1> -period <10.000> -waveform {2 8} {get_ports clk1} create_generated_clock create_generated_clock is used to constrain derived clocks … Read more
Click the blue text above to follow us 01 Basic Overview Acceleration Card Model: Inspur YPCB_00338_1P1 FPGA Chip Model: XC7K480TFFG1156-2 FLASH Chip Model: MT28GU512AAA1EGC-0SIT VIVADO Version: Vivado 2019.2 02 Program Burning In formal engineering projects, after generating the bitstream and verifying the solution, users will burn the official version of the program into FLASH. This … Read more
Introduction In the FPGA development process, programming the bitstream file and using ILA for debugging are common operations. However, if the FPGA board is located in a server room or connected to a server via PCIe, we often have to run to the server room or next to the server with a laptop to connect … Read more