The Artix 7 series FPGA provides many DSP hardware units that can be configured for floating-point operations.In the Vivado IP configuration interface, the clock cycle for the module can be selected, and data can be read out after a specified number of clock cycles.The Floating Point IP resource user manual from Vivado.However, it is somewhat … Read more
This series of instructional videos is led by Xilinx Senior Strategic Applications Engineers, guiding you from the ground up to master HLS and UltraFAST design methodologies, helping you become an expert in system design and algorithm acceleration! Course Update Schedule:Every second and fourth Tuesday of the month Mechanism of HLSLesson 2 As the saying goes, … Read more
Problem Description After downloading the elf file, a message box pops up as shown in Figure 1, indicating that there is a problem with the software operation. However, the software runs correctly; for instance, the VGA interface displays images normally, as shown in Figure 2. Moreover, this error does not appear in Debug mode. Figure … Read more
Win a Backpack How Difficult Is It? Give it a Try! →_→ Long Press to Recognize Copyright Statement: This article was published by the blogger“cuter”.Reprinting is welcome, but the content of the blog must not be altered, nor used for any profit purposes. When reprinting, the author’s profile and copyright statement must not be deleted. … Read more
Previously, it was explained that when external registers need to be added, the bus interconnection module must be changed. In the bus interconnection module, each register has a wire connected to the bus interconnection module for reading data and enabling signals. If there are relatively few registers, it seems there is no problem. But what … Read more
Vivado (Vitis) Version: 2020.2 FPGA Development Board: Microphase Z7-Lite 7020 Development Board FPGA Design Debugging Process FPGA development is an iterative process, and the general FPGA design process typically includes the following steps: Hardware architecture and algorithm verification: what modules are needed to implement the required functionality, how modules communicate and connect with each other; … Read more
Content Overview This article explains the process of creating an 8-channel high-performance logic analyzer. In this manual, we guide you to program the dedicated firmware we provide, allowing you to upgrade your BX71 core board into a high-performance logic analyzer with 500M sampling capability and 8 sampling channels, each with a storage depth of 400M. … Read more
Content Summary Previously, we released a high-performance logic analyzer with 8 channels and a 500M sampling rate based on the BX71 core board. Many users of the ACZ702 development board also hope we can provide firmware based on the ACZ702 development board. Today, we bring you this high-performance logic analyzer firmware and usage instructions based … Read more
Hello, hero! Welcome to the FPGA technology realm. The world of technology is vast, and meeting you is a fate. You can follow FPGA technology to get other interesting resources in the “Adventurous Journey” and “Chivalrous Acts” sections or enjoy a drink and chat together. “Enjoying a drink” enters the IC technology circle, where there … Read more
A Dual-Shoulder Backpack How Difficult Is It? Give It a Try! →_→ Long Press Recognition Circuits synthesized from FPGA are located inside the chip, making it nearly impossible to measure signals using oscilloscopes or logic analyzers. Therefore, manufacturers like Xilinx have invented built-in logic analyzers. In Vivado, this is called ILA (Integrated Logic Analyzer), whereas … Read more