Example of Designing an Optimal Equiripple FIR Digital Filter Using MATLAB

First, write out a normalized frequency vector and its corresponding magnitude vector, where the magnitude vector represents the desired amplitude-frequency characteristics. Set the order of the FIR digital filter, or use remezord() to calculate the order of the digital filter, and call remez() to design the FIR digital filter, which exhibits equiripple behavior in the … Read more

Introduction to FPGA Internal Resources: What is the Principle of Collaboration between LUT, FF, and BRAM?

The power of FPGA (Field Programmable Gate Array) lies in its integration of various programmable resources, enabling the flexible implementation of a wide range of digital circuits from simple logic to complex systems. Understanding the functions of these resources and their collaborative logic is fundamental to efficient FPGA design. 01 — Core Internal Resources of … Read more

Understanding Bluetooth Baseband: The Underlying Engine of Wireless Communication

Bluetooth technology, as a benchmark for short-range wireless communication, relies on a core module known as Baseband. This “digital brain” hidden at the bottom of the protocol stack is responsible for converting high-level data into radio signals that can traverse the 2.4GHz frequency band, while also handling critical tasks such as signal reception, error correction, … Read more

FPGA Tutorial Case 14: Design and Implementation of FIR Filter Based on Vivado Core

FPGA Tutorial Case 14: Design and Implementation of FIR Filter Based on Vivado Core

01Design and Implementation of FIR Filter Based on Vivado CoreThe Finite Impulse Response (FIR) filter is a widely used filter in the field of digital signal processing, known for its good stability, ease of implementation, and linear phase characteristics. The FIR filter is a linear time-invariant system composed of a set of coefficients, which performs … Read more

FPGA Tutorial Case 12: Design and Implementation of a Complex Multiplier Based on Vivado IP Core

FPGA Tutorial Case 12: Design and Implementation of a Complex Multiplier Based on Vivado IP Core

01Design and Implementation of a Complex Multiplier Based on Vivado IP CoreIn the fields ofdigital signal processing and image processing, complex multiplication is often required. A complex multiplier is a core component for performing this operation. Particularly in digital signal processing, complex multiplication has numerous applications, including signal mixing, FFT, and IFFT. The complex multiplier … Read more

Principles and Methods of Interference Resistance in Microcontroller Systems

Principles and Methods of Interference Resistance in Microcontroller Systems

With the development of microcontrollers, their applications in household appliances, industrial automation, production process control, and smart instruments are becoming increasingly widespread. However, various electrical devices within the same power system are closely interconnected through electrical or magnetic links, influencing each other. Electromagnetic oscillations caused by changes in operating modes, faults, or switching operations can … Read more

A Comprehensive Guide to DSP Chips (Must-Read)

A Comprehensive Guide to DSP Chips (Must-Read)

Source: Dongxing Securities DSP stands for Digital Signal Processing technology, and DSP chips refer to chips capable of implementing digital signal processing technology. DSP chips are a type of fast and powerful microprocessor, uniquely designed to process data instantly. The internal structure of DSP chips employs a Harvard architecture that separates program and data, featuring … Read more

Detailed Explanation of Binary Operations (Addition, Subtraction, Multiplication, Division) in FPGA

Detailed Explanation of Binary Operations (Addition, Subtraction, Multiplication, Division) in FPGA

In FPGA design, binary operations are one of the most fundamental and commonly used logical operations, with addition, subtraction, multiplication, and division widely applied in digital signal processing, control algorithms, and data computation scenarios. To simplify hardware implementation while accommodating signed operations, FPGAs typically use two’s complement representation for signed numbers. Using two’s complement not … Read more

FIR Filter Series: Joint Simulation Verification Platform for FIR IP using Matlab, Vivado, and Modelsim (Part 1)

FIR Filter Series: Joint Simulation Verification Platform for FIR IP using Matlab, Vivado, and Modelsim (Part 1)

1. Generating Input Waveforms for FIR IP in Matlab 2. Generating Filter Coefficients for FIR IP in Matlab In FPGA-based digital signal processing, data transfer and simulation verification between Matlab, Vivado, and Modelsim are required. The typical approach is for Matlab to generate input signals for the Verilog module as simulation stimuli, followed by testing … Read more

How to Simulate Fixed-Point Conversion for FPGA Using MATLAB Fixed-Point Toolbox

How to Simulate Fixed-Point Conversion for FPGA Using MATLAB Fixed-Point Toolbox

In digital signal processing and FPGA development, fixed-point design is a crucial step from algorithm to hardware implementation. Algorithms in MATLAB are typically modeled and verified using floating-point numbers, but FPGA hardware often only supports fixed-point operations. There are significant differences in data precision, rounding methods, and overflow handling between the two, leading to discrepancies … Read more