After completing the programming related to FPGA design, we need to write a tb file for functional verification. Here is a framework:
‘timescale 1ns/1ps
module tb_module_name();
/*
Input signals of the test module: signal types are defined as reg, ensure bit width consistency, ending with a semicolon
*/
/*
Output signals of the test module: signal types are defined as wire, ensure bit width consistency, ending with a semicolon
*/
Note: If you want to simulate intermediate signals in the test module, such as cnt etc., choose the appropriate variable type based on their requirements (sequential logic reg, combinational logic wire)
// Generate stimulus general template
initial begin
clk = 1’b1;
rst_n <= 1’b0;
#80
rst_n <= 1’b1;
etc….
end
always# 10 clk = ~clk;
module_name module_name_inst
(
.Input signal 1 of the test module (this module corresponds to signal 1),
.Input signal 2 of the test module (this module corresponds to signal 2),
.Input signal n of the test module (this module corresponds to signal n),
);
endmodule