FPGA Fixed-Point Decimal Calculation (Verilog) Part One

Here are the results from the past two days, implementing FPGA fixed-point decimal calculation in Verilog. There will be N parts, including addition, multiplication, division, square root, square, etc. Currently, addition and multiplication have been debugged, while division, square root, and square are not yet completed. Due to time constraints, this blog post will directly present the program, RTL structure diagram, and functional simulation waveform diagram. The explanation of the algorithm principles will be supplemented later when there is time.

FPGA Fixed-Point Decimal Calculation (Verilog) Part One – Addition Operation

First is qadd.v

FPGA Fixed-Point Decimal Calculation (Verilog) Part One

FPGA Fixed-Point Decimal Calculation (Verilog) Part One

Testbench file:

FPGA Fixed-Point Decimal Calculation (Verilog) Part One

FPGA Fixed-Point Decimal Calculation (Verilog) Part One

RTL view obtained after synthesis with Synplify Pro:

FPGA Fixed-Point Decimal Calculation (Verilog) Part One

ActiveHDL script file:

FPGA Fixed-Point Decimal Calculation (Verilog) Part One

ActiveHDL functional simulation waveform diagram:

FPGA Fixed-Point Decimal Calculation (Verilog) Part One

Note: Some of you may have already noticed, haha. The source code comes from Opencores, but I have fixed the bugs present in it…

FPGA Fixed-Point Decimal Calculation (Verilog) Part OneFPGA Fixed-Point Decimal Calculation (Verilog) Part One

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