Introduction — In FPGA-based image acquisition and display systems, large-capacity and high-speed memory is often required. Among various random access memory devices, SDRAM is an ideal choice due to its low cost, small size, high speed, and large capacity. However, the control logic of SDRAM is quite complex, and the timing requirements are very strict, … Read more
In FPGA design, frequency division is often required. For even frequency division, the code is relatively simple; the clock is inverted when the counter reaches half of the division factor, thus completing the even frequency division.For odd frequency division, the approach is slightly more complex. First, two temporary frequency division variables need to be defined: … Read more
Word count: 1092, reading time approximately 6 minutes Continuing from the last session, today we will implement the functionality of UART, primarily using the hardware description language Verilog. The interface design is actually quite simple. If we distill its essence, it can be divided into three main parts: data acquisition, state machine, and interface timing. … Read more
Introduction to Excellent Verilog/FPGA Open Source Projects (Thirteen) – I2C 0 Introduction to I2C Official Website ❝ I2C – What’s That? The I2C bus specification was written by Philips Semiconductors, which later became NXP Semiconductors, and is now the maintainer of the I2C bus specification. Unfortunately, the latest I²C bus specification, NXP document version 6.0, … Read more
I have been writing RTL for over a decade and have encountered various engineering coding standards, constraints, and suggestions. Therefore, I am summarizing my experiences at this stage. The Verilog/SV coding suggestions and some engineering requirements mentioned and discussed in this series are based on what I have encountered and understood during my work process. … Read more