SOC Design (3) – Starting from SOC System Boot

SOC Design (3) - Starting from SOC System Boot

Before discussing the boot process, let’s briefly talk about the learning path for digital ICs. There are many directions in digital IC design, including processor chip design, memory chip design, logic chip design, and so on. Ultimately, we find that digital chip systems generally encompass three functions: storage, transmission, and computation. The value of a … Read more

FPGA in the Blue Bridge Cup | Is This the Correct Way to Map Bidirectional Ports in Verilog?

FPGA in the Blue Bridge Cup | Is This the Correct Way to Map Bidirectional Ports in Verilog?

The Verilog implementation of bidirectional ports provided in the resource package is as follows:The synthesized schematic is as follows:The original author’s IIC driver implementation of bidirectional ports is as follows, which is also a common practice in our actual work:The synthesized schematic is as follows:The schematics generated from both implementations are the same, with version … Read more

FPGA Tutorial Case 58: Deep Learning Case 5

FPGA Tutorial Case 58: Deep Learning Case 5

01Deep Learning Case 5 – Verilog Implementation of Image Buffer for CNN Convolutional Neural Network Based on FPGA This tutorial provides a detailed introduction to the Verilog implementation of the image buffer layer for CNN convolutional neural networks based on FPGA. The content includes software versions, theoretical introduction to image buffering, Verilog code implementation, and … Read more

FPGA Tutorial Case 61: Hardware Development Board Debugging 1

FPGA Tutorial Case 61: Hardware Development Board Debugging 1

01Hardware Development Board Debugging 1 – Introduction to FPGA Development Boards, controlling LED lights and switches using VerilogUsing Vivado 2019.2, this article introduces the use of the Spartan7 FPGA development board, including the writing of pin constraint files, synthesis, layout, routing, and hardware download testing steps. By writing a Verilog program to control the LED … Read more

How Undergraduates Can Enter the FPGA Field

How Undergraduates Can Enter the FPGA Field

For undergraduates, entering the FPGA development field requires systematic planning and practical accumulation. Below is a grounded guide summarized from industry experience to help you start from scratch: 1. Solidify the Basics: Build a knowledge framework with core courses covering essential content: Digital Circuits (Digital Logic), Computer Architecture, and Interface Technology. Recommended book: Fundamentals of … Read more

Eliminating Screen Tearing! FPGA Video Buffer Design (Part 1): Writing a Ping-Pong Controller from Scratch

Eliminating Screen Tearing! FPGA Video Buffer Design (Part 1): Writing a Ping-Pong Controller from Scratch

0. Visual ChinaVisual China Contracted Photographer Horizon – Little Train1. Introduction: Why Use Buffers?Many FPGA beginners think that when processing video, the most straightforward idea is: the data from the camera can be directly sent to the HDMI display module, right?This “direct connection” method only works under an extreme coincidence: the output clock of the … Read more

FPGA-Based AD7705 Driver Design Verilog Code Simulation

FPGA-Based AD7705 Driver Design Verilog Code Simulation

Name: FPGA-Based AD7705 Driver Design Verilog Code Simulation Software: Quartus Language: Verilog Code Function: AD7705 Driver Design 1. Project Files 2. Program Files 3. Program Compilation 4. Simulation Diagram Testbench Simulation Diagram Overall Simulation Reset, continuously write 32 high levels Sequentially write 8’h20, 8’h03, 8’h10, 8’h40 Write 8’h38, and read data Partial code display: module … Read more

FPGA Tutorial Case 59: Deep Learning Case 6

FPGA Tutorial Case 59: Deep Learning Case 6

01Deep Learning Case 6 – Overall Implementation of CNN Convolutional Neural Network Based on FPGA This tutorial provides a detailed introduction on how to implement a CNN convolutional neural network on FPGA, including the image input layer, convolutional layer, activation layer, and pooling layer. Using Verilog programming, it gradually constructs the overall structure of the … Read more

Design of a Simple Equal Precision Frequency Counter Based on FPGA: Verilog Code and ISE Simulation

Design of a Simple Equal Precision Frequency Counter Based on FPGA: Verilog Code and ISE Simulation

Name: Design of a Simple Equal Precision Frequency Counter Based on FPGA: Verilog Code and ISE Simulation Software: Quartus Language: Verilog Code Function: Simple equal precision frequency counter design Requirements Measured Signal: TTL Square Wave A. Frequency Measurement Range: 100Hz ~ MHz B. Measurement Error: ≤0.1% (full scale); C. Clock Frequency: 50kHz D. Pre-gate Time: … Read more

FPGA-Based Washing Machine Controller Design Verilog Code for Quartus and Zedboard

FPGA-Based Washing Machine Controller Design Verilog Code for Quartus and Zedboard

Name: FPGA-Based Washing Machine Controller Design Verilog Code for Quartus and Zedboard Software: Quartus Language: Verilog Code Function: The main tasks and basic requirements are as follows: 1. Main Tasks Design and implement an FPGA-based washing machine controller using Verilog or VHDL for hardware description. The controller should enable intelligent control of the washing machine’s … Read more