Welcome FPGA engineers to join the official WeChat technical group Clickthe blue textto follow us at FPGA Home – the largest and best FPGA pure engineer community in China Introduction: In this article, we introduce the global clock resources. The global clock is a dedicated interconnect network specifically designed to reach all clock inputs to … Read more
Welcome FPGA engineers to join the official WeChat technical group Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineering community in China LVDS stands for Low-Voltage Differential Signaling. The selectIO of FPGA is very powerful, supporting various IO interface standards, with voltage and current configurable. Its interface rate … Read more
Xilinx 7 Series FPGAs are composed of four categories, addressing the complete system requirements from low-cost, small size, cost-sensitive, high-capacity applications to the most demanding high-performance applications with ultra-high-end connectivity bandwidth, logic capacity, and signal processing capabilities. First, let’s take a look at the naming conventions for Xilinx 7 Series FPGAs. 01 Spartan-7 Series Optimized … Read more
Welcome FPGA engineers to join the official WeChat technical group. This article mainly introduces the configuration modes of Xilinx FPGAs, including Master/Slave mode, Serial/SelectMAP mode, JTAG mode, etc. Among them, the 7 series only has the Logic part, and all configuration-related function pins are connected to specific banks on the FPGA side; the Zynq 7000 … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the largest and best pure FPGA engineer community in China. This article mainly introduces the I/O resources on the PL side of Xilinx FPGA, which currently includes three types: HP, HR, and HD. Different architectures and … Read more
1. Overview Xilinx FPGAs starting from the 7 series have on-chip Advanced Encryption Standard (AES) decryption logic, providing a high level of design security. Encrypted Xilinx FPGA designs cannot be copied or reverse-engineered for other FPGAs.The Xilinx FPGA responsible for encryption uses an AES system consisting of software-based bitstream encryption and on-chip bitstream decryption, with … Read more
Although the AXI interface is frequently used, many may not be aware that Vivado also integrates AXI Verification IP, which can serve as an AXI master, pass-through, and slave. In this content, we will explore how to use the AXI VIP as a master. Create a new Vivado project and a new block design named: … Read more
In the past two years, opportunities for industry development have emerged from chip design to upstream materials and equipment, and down to downstream distributors. Among them, KeTong Technology is one of the domestic electronic component distributors and has performed exceptionally in the market. The company closely collaborates with several leading chip manufacturers globally, covering major … Read more
Recently, our company has been preparing for the FPGA localization plan and conducting market research. We have also arranged discussions with market engineers from several domestic FPGA manufacturers.Regarding FPGA, I consider myself a latecomer. After graduating, I worked on MCU development for about a year, and later, due to project needs, I started to engage … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. Comprehensive Attributes In the Vivado Design Suite, the Vivado synthesis can synthesize various types of attributes. In most cases, these attributes have the same syntax and … Read more