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Comprehensive Attributes
In the Vivado Design Suite, the Vivado synthesis can synthesize various types of attributes. In most cases, these attributes have the same syntax and the same behavior.
• If the Vivado synthesis supports the attribute, it will use it and create logic reflecting the attribute used.
• If the tool cannot recognize the specified attribute, the Vivado synthesis will pass the attribute and its value to the generated netlist.
1. ASYNC_REG
ASYNC_REG is an attribute that affects many processes in the Vivado tool flow. The purpose of this attribute is to inform the tool that the register can receive asynchronous data relative to the source clock at the D input pin, or that the register is a synchronous register in a synchronous chain.
When this attribute is encountered, the Vivado synthesis will treat it as a DONT_TOUCH attribute and will forward the ASYNC_REG attribute in the netlist. This process ensures that objects with the ASYNC_REG attribute are not optimized, and later tools in the flow will receive the attribute to handle it correctly.
You can place this attribute on any register; the value can be FALSE (default) or TRUE. This attribute can be set in RTL or XDC.
ASYNC_REG Verilog Example:
(*ASYNC_REG = “TRUE” *) reg [2:0] sync_regs;
2. CLOCK_BUFFER_TYPE
Apply CLOCK_BUFFER_TYPE on the input clock to describe the type of clock buffer to be used.
By default, the Vivado synthesis uses BUFG as the clock buffer. Supported values are “BUFG”, “BUFH”, “BUFIO”, “BUFMR”, “BUFR” or “none”. The CLOCK_BUFFER_TYPE attribute can be placed on any top-level clock port. It can be set in RTL and XDC.
CLOCK_BUFFER_TYPE Verilog Example:
(* clock_buffer_type = “none” *) input clk1;
CLOCK_BUFFER_TYPE XDC Example:
set_property CLOCK_BUFFER_TYPE BUFG [get_ports clk]
3. FSM_ENCODING
FSM_ENCODING controls the encoding on the state machine. Typically, the Vivado tool selects an encoding protocol for the state machine based on heuristics that best suit most designs. Certain types of designs work better with specific encoding protocols.
FSM_ENCODING can be placed on state machine registers. Its valid values are “one_hot”, “sequential”, “johnson”, “grey”, “auto” and “none”. The “auto” value is the default, allowing the tool to determine the best encoding. This attribute can be set in RTL or XDC.
FSM_ENCODING Example (Verilog):
(* fsm_encoding = “one_hot” *) reg [7:0] my_state;
4. KEEP
Using the KEEP attribute prevents signals from being optimized or absorbed into logic blocks during optimization. This attribute instructs the synthesis tool to keep the signal it is associated with and include that signal in the netlist.
For example, if the signal is the output of a 2-bit AND gate and it drives another AND gate, the KEEP attribute can be used to prevent that signal from being merged into a larger LUT that contains both AND gates.
KEEP is also commonly used for timing constraints. If there are timing constraints on a signal that would normally be optimized, KEEP will prevent that operation and allow the correct timing rules to be used.
KEEP Example (Verilog):
(* keep = “true” *) wire sig1;
assign sig1 = in1 & in2;
assign out1 = sig1 & in2;
5. RAM_STYLE
RAM_STYLE indicates how the Vivado synthesis tool infers memory. Acceptable values are:
• block: indicates the tool infers RAMB type components.
• distributed: indicates the tool infers LUT RAM.
• register: indicates the tool infers registers instead of RAM.
• ultra: indicates the tool uses UltraScale +™ URAM primitives.
By default, the tool selects which RAM to infer based on heuristics to provide the best results for most designs. This attribute should be placed on the array or hierarchical level declared for RAM.
• If set on a signal, this attribute will affect that specific signal.
• If set at the hierarchical level, it will affect all RAM at that hierarchical level.
Sub-levels of the hierarchy are not affected.
This can be set in RTL or XDC.
RAM_STYLE Example (Verilog):
(* ram_style = “distributed” *) reg [data_size-1:0] myram [2**addr_size-1:0];
6. ROM_STYLE
ROM_STYLE indicates how the synthesis tool infers ROM memory. Acceptable values are:
• block: indicates the tool infers RAMB type components.
• distributed: indicates the tool infers LUT ROM. By default, the tool selects which ROM to infer based on heuristics to provide the best results for most designs.
This can be set in RTL and XDC.
ROM_STYLE Example (Verilog):
(* rom_style = “distributed” *) reg [data_size-1:0] myrom [2**addr_size-1:0];
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