From C Language to VHDL: Bridging the Gap Between Software and Hardware Thinking

Today, we will discuss the hardware design knowledge that every software programmer needs to understand, especially for those who are just starting to engage in hardware design.

For developers who are already familiar with programming languages like C or Java, they often encounter misunderstandings when learning hardware description languages such as VHDL or Verilog.

This article explains these misunderstandings and illustrates the differences between the software world and the hardware world through code examples.

Assumption 1: Serial Logic vs. Parallel Logic

This is the most fundamental difference between hardware programming and software programming.

Software developers are accustomed to serial code, which means that each line of code must wait for the previous line to finish executing before it can execute.

For example, in C language, line 2 can only execute after line 1 has completed.

In contrast, VHDL and Verilog are parallel logic languages, where each line of code can execute simultaneously, meaning they are executed in parallel.

For instance, if a designer wants to light up an LED every 10 clock cycles, the software code might look like this:

Software Code:

while (1) {  if (count == 9) {    LED_on = 1;    count = 0;  } else {    LED_on = 0;    count = count + 1;  }}

VHDL Code:

P_INCREMENT : process (clock)begin  if rising_edge(clock) then    if(count < 9) then      count <= count + 1;    else      count <= 0;    end if;  end if;end process P_INCREMENT;LED_on <='1' when count = 9 else '0';

<span><span>In software, each line of code is executed sequentially, while in VHDL, the assignment of LED_on occurs in parallel with the VHDL process. Therefore, we must remember that VHDL and Verilog are parallel languages.</span></span>

Assumption 2: For Loops

For many novice hardware developers,<span><span>for</span></span> loops can be a significant issue because they are accustomed to the <span><span>for</span></span> loops in C language.

It is important to clarify that in hardware, the behavior of a <span><span>for</span></span> loop is completely different from that in software.

Until you understand how the <span><span>for</span></span> loop works, it should not be used in hardware design.

Software Code:

for (int i = 0; i < 10; i++){  data[i] = data[i] + 1;}

VHDL Code:

P_INCREMENT : process (clock)begin  if rising_edge(clock) then    if (index < 10) then      data(index) <= data(index) + 1;      index <= index + 1;    end if;  end if;end process P_INCREMENT;

Here, it can be seen that the number of lines of code required to achieve similar functionality in C language is fewer, while in VHDL, it typically requires more code to achieve the same functionality.

For those just starting in hardware design, it is not recommended to use <span><span>for</span></span> loops, but rather to implement similar functionality by adding counter signals.

Assumption 3: Code Execution is Instantaneous

In software, code execution is instantaneous, but this is not the case in hardware.

In hardware design, code does not execute immediately, nor does it update the value of signals immediately. The following example demonstrates the error in this assumption:

Software Code:

state = INITIALIZE;data = 5;state = LOAD_1;data = 6;state = LOAD_2;data = 1;state = DONE;data = 0;

Incorrect Hardware Code:

P_STATE_MACHINE : process (clock)begin  if rising_edge(clock) then    state <= INITIALIZE;    data <= 5;    state <= LOAD_1;    data <= 6;    state <= LOAD_2;    data <= 1;    state <= DONE;    data <= 0;  end if;end process P_STATE_MACHINE;

In this incorrect hardware code, because each line of code is executed in parallel, it results in <span><span>data</span></span> always remaining 0, while the state remains stuck in the DONE state.

The correct hardware code should be:

Correct Hardware Code:

P_STATE_MACHINE : process (clock)begin  if rising_edge(clock) then    if (state == INITIALIZE) then      data <= 5;      state <= LOAD_1;    elsif (state == LOAD_1) then      data <= 6;      state <= LOAD_2;    elsif (state == LOAD_2) then      data <= 1;      state <= DONE;    elsif (state == DONE) then      data <= 0;    else      state <= INITIALIZE;    end if;  end if;end process P_STATE_MACHINE;

For new hardware designers, understanding the differences in parallel logic, the <span><span>for</span></span> loop, and the delays in code execution is very important.

Once you grasp these fundamental concepts, you will be better equipped for hardware design.