Have you ever encountered a situation where you want to share your code with someone else, but you only want them to use it without having access to the source code? In this case, you can provide them with the netlist file of your code.In this way, they will have usage rights but no modification rights.So, what is a netlist? And how is it generated?First, let’s answer what a netlist is.When I graduated and started working, my supervisor asked me and another recent graduate to choose our positions. One was to write microcontroller programs, and the other was to learn Cadence.I chose Cadence. When using Cadence to design PCBs, the files sent to the fabrication house are not our PCB source files but rather the netlist files.The netlist files we discuss today are generated based on similar principles.The code we write is ultimately transformed into a BIT file that is downloaded to the chip, and this transformation is well-known to occur through synthesis, placement, and routing.Synthesis translates the code written in Verilog into circuit components, such as flip-flops and logic gates.Placement involves arranging the synthesized logic components in suitable locations on the chip.Routing connects the various electronic components with interconnecting wires.Finally, the circuit is generated.The netlist is the circuit generated after synthesis.By providing the netlist to others, they cannot see the source code or modify it, but they can use it.It is said that some skilled engineers can reverse-engineer code from a netlist; I have not researched this yet, but feel free to leave comments for discussion.Next, let’s answer how to generate a netlist.Step 1: Set the module for which we want to generate the netlist as the top layer.As shown in the figure below, I set flash_rw_test as the top layer, which instantiates other modules, including a Xilinx IP core.
Step 2: Modify the synthesis settings.Modify as shown in the figure below; the purpose of this modification is to flatten the project’s hierarchical structure. In other words, my project has a two-layer structure, with the top layer being flash_rw_test, and there are other modules beneath it. After modifying according to the method shown in the figure, others will not see this hierarchical structure. I guess this is also a way to prevent so-called experts from guessing or reverse-engineering the code from the netlist file, but I am not entirely sure.
In the more options section, enter: -mode out_of_context. This prevents the addition of IO buffers on the IOs. Since the netlist files we generate are generally instantiated as small modules rather than used as top-level modules, if there are IO buffers on the interface, it will cause errors during netlist instantiation. By modifying this setting, there will be no IO buffers.
Step 3: Start synthesis.
Step 4: Open synthesis.
Step 5: Generate the interface fileandthe netlist fileby entering the following two commands in the TCL command window:
write_verilog -mode synth_stub pcie_top.v
write_edif -security_mode all pcie_top.edf
The first command:write_verilog -mode synth_stub xx.v is used to generate the interface file, where xx.v is the name of the interface file, for example, my interface file is named pcie_top.v.
The second command:write_edif -security_mode all xx.edf is used to generate the netlist file, where xx.edf is the name of the generated netlist file.
After entering these two commands, the netlist file and interface file will be generated, and you can copy them to the specified location. The specific path is shown in the figure below. You can also specify a path to generate the netlist file and interface file in a designated location. However, I generally do not do this, as it complicates the above two commands. I usually let the netlist file and interface file generate in the default location. The default location on my computer is shown in the figure below.
After the netlist is generated, how do you use it?
1. First, add the netlist file and interface file to the project.
2. Instantiate the netlist file.
Simply copy the interface from the interface file and instantiate it.
This step is too simple to explain further.
Done.
Everyone, go ahead and give it a try!