Name: Simple Digital Clock Design Based on FPGA: VHDL Code and Quartus Simulation Software: Quartus Language: VHDL Code Function: Simple digital clock design 1. Design a base-24 counter, which can adjust the count value using buttons. 2. Design a base-60 counter, which can adjust the count value using buttons. 3. Design a display module. 4. … Read more
Name: Design of a Simple Equal Precision Frequency Counter Based on FPGA: Verilog Code and ISE Simulation Software: Quartus Language: Verilog Code Function: Simple equal precision frequency counter design Requirements Measured Signal: TTL Square Wave A. Frequency Measurement Range: 100Hz ~ MHz B. Measurement Error: ≤0.1% (full scale); C. Clock Frequency: 50kHz D. Pre-gate Time: … Read more
Name: FPGA-Based Washing Machine Controller Design Verilog Code for Quartus and Zedboard Software: Quartus Language: Verilog Code Function: The main tasks and basic requirements are as follows: 1. Main Tasks Design and implement an FPGA-based washing machine controller using Verilog or VHDL for hardware description. The controller should enable intelligent control of the washing machine’s … Read more
Name: UART Asynchronous Serial Communication Circuit Design Verilog Code for Quartus FPGA_C4_V2.1 Experimental Board Software: Quartus Language: Verilog Code Function: Function Description Enhance the transmission rate of UART communication, supporting higher baud rates (such as 115200, 230400, or higher). Implementation Method 1. Optimize Baud Rate Division Use a higher system clock frequency (e.g., 100MHz) and … Read more
Name: LCD1602 Module Driver Code Design in Verilog for Quartus Development Board Software: Quartus Language: Verilog Code Function: Design of the LCD1602 module driver code 1. Using Quartus software 2. Using Verilog language 3. Input two sets of 16-bit binary data, allowing the LCD1602 to display the string “consume” along with the first group of … Read more
Name: UART Serial Transmission and Reception String Design Verilog Code Quartus Simulation Software: Quartus Language: Verilog Code Function: UART serial transmission and reception of strings Simulated transmission string “from my RISC-V SoC UART !!!!!!” 1. Project Files Edit 2. Program Files Edit 3. Testbench Edit 4. Simulation Diagram Edit Partial Code Display: `timescale 1ns / … Read more
In the design of complex systems such as 5G wireless, satellite communication, radar detection, and aerospace control, FPGA engineers play a crucial role. For an FPGA team, it is essential to complete the product design and verification according to project requirements, ensuring project delivery. To maintain efficient communication and progress among FPGA engineers in increasingly … Read more
Click the blue text to follow, grateful for your support Welcome friends to follow“Hao Xushuang Electronic Design Team” public account, this account will regularly update relevant technical materials, software, etc. Friends who are interested can browse other“modules”, hoping that everyone can gain something they desire from this public account“things”. This article mainly discussesthe two modes … Read more
Introduction This document mainly introduces the configuration and considerations of the GRMII, RGMII, and SGMII interfaces for the Quartus platform Triple-Speed Ethernet Intel FPGA IP. The version of the Quartus platform is Quartus Prime Pro 22.3. The FPGA device is Arria 10. The hardware mode is 1000BASE-T. GMII Core Configurations Configuration Interface Select MAC type … Read more
Follow the blue text and reply “entry materials” to get a comprehensive tutorial from beginner to advanced on microcontrollers The development board will guide you, we will help you fly Written by | Wuji (WeChat: 2777492857) The full text is about1507 words, reading will take about 5 minutes I have been doing microcontroller development, but … Read more