UART Serial Transmission and Reception String Design Verilog Code Quartus Simulation

Name: UART Serial Transmission and Reception String Design Verilog Code Quartus Simulation

Software: Quartus

Language: Verilog

Code Function:

UART serial transmission and reception of strings

Simulated transmission string “from my RISC-V SoC UART !!!!!!”

1. Project Files

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2. Program Files

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3. Testbench

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4. Simulation Diagram

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Partial Code Display:

`timescale 1ns / 1ps module tb_uart_send(); // Define simulation parameters localparam  CLK_PERIOD = 20;     // System clock period 20ns (50MHz) localparam  BAUD_RATE  = 115200; // UART baud rate localparam  BIT_PERIOD = 1000000000 / BAUD_RATE; // Time per bit (ns) // Define string content localparam  STRING_LEN = 28; // String length reg [7:0]   send_data [0:STRING_LEN-1]; // Store string ASCII codes // Define module interface signals reg         sys_clk; reg         sys_rst_n; reg         uart_en; reg  [7:0]  uart_din; wire        tx_done; wire        uart_txd; // Instantiate the module under test uart_send u_uart_send (     .sys_clk     (sys_clk),     .sys_rst_n   (sys_rst_n),     .uart_en     (uart_en),     .uart_din    (uart_din),     .tx_done     (tx_done),     .uart_txd    (uart_txd) ); // Initialize string ASCII codes (direct assignment) initial begin     send_data[0]  = "F";  // Decompose string     send_data[1]  = "r";     send_data[2]  = "o";     send_data[3]  = "m";     send_data[4]  = " ";     // ... Fill in all characters sequentially (remaining characters need to be completed here)     send_data[27] = "!";  // Last character '!' end