FPGA-Based Electronic Quiz Buzzer Design Verilog Code Quartus Simulation

Name: FPGA-Based Electronic Quiz Buzzer Design Verilog Code Quartus Simulation

Software: Quartus

Language: Verilog

Code Function:

FPGA-Based Electronic Quiz Buzzer

This design is an FPGA-based four-channel intelligent quiz buzzer, featuring system reset, a 30-second countdown, and digital tube display functions. The buzzer is implemented through four main modules: debouncing, control, score management, and display control, making it suitable for competitive events. It supports host control and contestant buzzing, with the ability to latch and display the successful contestant’s number and score.

1. Project Files

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2. Program Files

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3. Program Compilation

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4. RTL Diagram

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5. Simulation Diagram

Overall Simulation Diagram

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Debouncing Module

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Control Module

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Timing Module

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Score Control Module

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Digital Tube Display Module

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Partial Code Display:

//Buzzer Control Module
module qiangda_ctrl(
    input clk,
    input reset_n,//Reset buzzer state
    input start_p,//Start control button
    //4 buzzer buttons
    input key_1,
    input key_2,
    input key_3,
    input key_4,
    //4 indicator lights for 4 contestants
    output reg led_1,
    output reg led_2,
    output reg led_3,
    output reg led_4,
    output reg led_tiqian,//Early buzzer alarm
    output reg led_overtime,//Timeout alarm
    output [4:0] state_out,//Output state
    input [7:0] time_done,//Countdown
    output reg beep,//Buzzer success tone
    output [3:0] tiqian_qiangda,//Early buzzer
    output [3:0] qiangda//Normal buzzer
);
    parameter s_idle=5'd0;
    parameter s_start=5'd1;
    parameter s_timedown=5'd2;
    parameter s_tiqian_1=5'd3;
    parameter s_tiqian_2=5'd4;
    parameter s_tiqian_3=5'd5;
    parameter s_tiqian_4=5'd6;
    parameter s_qianda_1=5'd7;
    parameter s_qianda_2=5'd8;
    parameter s_qianda_3=5'd9;
    parameter s_qianda_4=5'd10;
    parameter s_overtime=5'd11;
    reg [4:0] state=5'd0;
    reg [7:0] time_cnt=8'd20;
    assign state_out=state;
    always@(posedge clk or negedge reset_n)
        if(!reset_n)
            state <= s_idle;
        else case(state)
            s_idle://Idle state, buzzer not started yet
                if(start_p)//Start buzzer button
                    state <= s_start;
                else