If you want to create a SOC chip, self-develop customized IP to highlight differentiation, and purchase other general-purpose IP, then just connect them together. Making a SOC is just about connecting the dots. Once the Verilog code is finished, is the chip ready for tape-out? Let’s not even talk about the technology of connecting the SOC; what happens after everything is connected?
First, you need to compile successfully, organize the file list, sub-modules, subsystems, and top-level, integrating from the bottom up. Run the RTL compile, clearing all errors. Once the compilation passes, clear all warnings. No errors, no warnings!
Then you need to clear Lint, cleaning sub-modules, subsystems, and top-level, eliminating all errors and warnings. If you can’t clear them, waive them. No errors, no warnings!
Why aim for no warnings? Because many bugs may be hidden in warnings; fixing them reduces the number of bugs during verification.
Release the version for verification.
Generate SDC, write per block, and the top-level should only output top SDC. Run pre-synthesis, clean logs and reports of all errors, and sweep all warnings. Deliver the block and the top. The top-only pre-synthesis should include the block’s lib/db; to speed up early delivery, a fake lib/db can be generated using scripts. The top can be delivered in parallel with the block. Deliver the sync cell list and don’t touch list.
Generate UPF, describing low power and power schemes, with block UPF, top-level UPF, and flat UPF. Generate the ISO list. Run CLP/VCLP to ensure UPF syntax and semantics are correct, and that domain divisions have no conflicts. Later, perform power analysis and optimization.
Run Formal, under normal circumstances, RTL vs. netlist should pass in one go; if not, either your RTL has issues, or the synthesis constraints are unreasonable and need to be supplemented.
Run DFT VCLINT, write SGDC constraints, describing OCC points, test_rstn points, test mode, and clk mux points. Clear errors and warnings, which can resolve 80% of the uncontrolled issues with register clocks and resets in DFT mode. Deliver no scan list, no wrapper list, and TDR list.
Run CDC/RDC checks, per block, top-only, and full chip flat checks. Waive, no errors, no warnings!
Release the version to the mid-end.
In the mid-to-late stages, address DFT feedback issues by adding test_mux and TDR, supplementing unreasonable SDC constraints, increasing timing paths that are too long, and modifying solutions or UPF for low power that cannot be achieved, as well as modifying RTL for congestion issues.
Verification debug, EDA, EMU, FPGA, DFT, low power, post-simulation verification debug. Coverage analysis, generate waive files, achieving “explainable” 100%.
STA analysis, block STA, full chip flat STA. Generate flat SDC, modify unreasonable SDC, and iterate RTL for timing that cannot be achieved.
STC, special timing check, provides path checks to see if they meet expectations, and violations should be fixed.
RTL Freeze.
ECO, manual ECO or tool automated ECO flow.
Once the Verilog code is completed, is the chip ready for tape-out? Well, this is just the first step. Note: This article only covers front-end work; mid-to-late stage work has not been addressed. To be continued~