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Fanout refers to the number of lower-level modules directly called by a module. If this value is too large, it directly manifests as a large net delay in FPGA, which is not conducive to timing convergence. Therefore, when writing code, one should try to avoid high fanout situations. However, in certain special cases, due to the needs of overall structural design or limitations on modifying the code, it is necessary to solve the problems caused by high fanout through other optimization methods. Here are three such methods:
First, let’s look at the following example. As shown in Figure 1, it is the timing report of the critical path in a transposed FIR filter. In the FIR topic of DSP in FPGA, it is mentioned that the fanout of the input data in a transposed structure FIR filter is relatively large, as shown in Figure 1 with a value of 11, resulting in a net delay of 1.231ns. As shown in Figure 2, the input data drives 11 DSP48E1s.
Without optimization, the fmax of this design is: 206.016MHz.
1. Register Duplication
Register duplication is one of the most commonly used methods to solve high fanout problems. By duplicating several identical registers, the task of driving all modules by the original single register can be shared, thereby reducing the fanout. By simply modifying the code, as shown in Figure 3, four registers were duplicated: din_d0, din_d1, din_d2, din_d3. din_d, din_d0, din_d1, and din_d2 each drive 2 DSP48E1s, while din_d3 drives 3 DSP48E1s. In the code, to prevent the synthesizer from optimizing the same registers, the (* EQUIVALENT_REGISTER_REMOVAL=”NO” *) attribute was added to the corresponding signals to avoid optimization.
After synthesis, the timing report obtained is shown in Figure 4. The fanout of the input data on this data path is reduced to 2, and the corresponding net delay is also reduced to 0.57ns. The design is shown in Figure 5, which is the same as expected, where 4 registers were duplicated to share the fanout. After register optimization, the fmax is: 252.143MHz.
2. max_fanout Attribute
In the code, you can set signal attributes and set the max_fanout attribute of the corresponding signal to a reasonable value. When the fanout of this signal exceeds this value in the actual design, the synthesizer will automatically apply optimization methods to this signal, which commonly involves register duplication. The attribute is set as shown in the following code:
(* max_fanout = “3” *) reg signed [15:0] din_d;
Setting the max_fanout attribute of the din_d signal to 3, after synthesis, the timing report obtained is shown in Figure 6, where the fanout is only 2, and the corresponding net delay is only 0.61ns, indicating a good automatic optimization effect. The structure is shown in Figure 7, where din_d_12_1, din_d_12_2, and din_d_12_3 are automatically added by the synthesizer, achieving the function of register duplication. After optimizing with the max_fanout attribute, the fmax is: 257.135MHz.
3. BUFG
Typically, BUFG is a resource used for global clocks and can solve issues arising from high fanout signals. However, it is generally used for signals with super large fanout, such as clocks or resets, where the logic involved spans the entire chip. BUFG can optimize routing from a global perspective. Moreover, the BUFG resources are limited in a single FPGA chip; for example, there are only 32 on a 7k325tffg900. Therefore, using BUFG for high fanout optimization of ordinary signals is not very realistic. Thus, using BUFG for clocks is essential, but if certain reset signals face timing issues due to high fanout in the design, BUFG can be used to optimize those signals.
In summary, when encountering high fanout signals, register duplication or setting the max_fanout attribute can be used for ordinary signals; for reset signals, BUFG can be added for optimization.
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