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Continuing from the previous article:Xilinx 7 Series FPGA High-Speed Transceiver TX Transmitter Introduction
The previous blog introduced the GTX transmitter, and this article will introduce the GTX RX receiver. The structure of the GTX RX receiver is similar to the TX transmitter, but the data flow direction is reversed. However, there are some differences from the transmitter. The structure diagram of the GTX RX receiver is shown in Figure 1:
Figure 1
Below, we will introduce the functions of each circuit part of the RX receiver based on the data flow direction.
RX Equalizer (DFE and LPM): The RX signal enters from the AFE (analog front-end) and first goes through the RX equalizer. The main function of the equalizer is to compensate for the high-frequency loss of the signal during channel transmission. Since the channel has limited bandwidth, the signal will inevitably suffer attenuation or even damage after passing through it.
The RX receiver has two types of equalizers, namely LPM and DFE, which differ in power consumption and performance. The LPM has lower power consumption, while the DFE can provide more accurate filter parameters, thereby better compensating for transmission channel losses and thus offering better performance.
RX CDR: The RX clock data recovery circuit is the green circle part in Figure 1. Since GTX transmission does not carry a clock signal, the receiver must perform clock recovery and data recovery on its own. The clock data recovery circuit is shown in Figure 2:
Figure 2
The specific process is shown in Figure 2. First, the external data comes in and passes through the equalizer. Then, the data from the equalizer enters the clock data recovery circuit. GTX uses a phase-rotating CDR structure. The data coming from the DFE is captured by both the edge sampler and data sampler, and then the CDR state machine determines the phase of the data flow based on the two and feeds back to control the phase interpolator ( PI). When the position of the data sampler is at the center of the eye diagram, the edge sampler locks onto the transmission domain of the data flow. The CPLL or QPLL provides the base clock for the phase interpolator, allowing the CDR state machine to perform phase control effectively.
RX Fabric Clock Output Control: The clock structure of the RX receiver is very similar to that of the TX transmitter, as shown in Figure 3. The CDR part in the red box in the figure is the biggest difference from the TX side.
Figure 3
Similar to the TX transmitter, the RX receiver’s clock structure is also mainly divided into serial clock divider and parallel clock divider. The D divider is the serial clock divider, used to reduce the PLL clock rate to support lower line rates. The subsequent parallel clock divider mainly generates different parallel data clocks based on the configured bit width and whether to use 8b/10b encoding.
RX Polarity Control: Like the TX transmitter, the RX receiver also has a polarity control function that can be used to implement data flipping. This function is used when RXP and RXN are reversed during PCB design.
RX Pattern Checker: GTX includes an embedded PRBS checker, as shown in Figure 4. There are four different pseudo-random sequence generators to choose from. The checker is self-synchronizing and operates before boundary alignment and decoding. This function can be used to test the integrity of the signal.
Figure 4
RX Byte and Word Alignment: Before serial data is parallelized, it needs to find a suitable feature boundary. This feature boundary or character boundary is a recognizable sequence sent by the TX transmitter, usually referred to as an identifier ( comma) or K code. The receiver searches for this identifier in the incoming data. Once this identifier is found, the subsequent received data is parallelized based on this identifier as the boundary. Its working principle is shown in Figure 5.
Figure 5
As shown in Figure 5, when the comma is found in the serial data (red box), the subsequent data is aligned based on this boundary.
RX 8B/10B Decoder:If the data sent by the transmitter is 8B/10B encoded, then the receiver needs to 8B/10B decode it; otherwise, it can be bypassed. This function was explained when introducing the TX transmitter, so it will not be elaborated here.
RX Elastic Buffer: The RX receiver’s elastic buffer is an important function. Compared to the TX receiver buffer, the RX has an “elastic” property, meaning it has more functions than the TX transmitter ( RX clock correction and RX channel bonding). The RX elastic buffer is located as shown in the green box in Figure 6.
Figure 6
From Figure 6, it can be seen that the RX receiver PCS sublayer mainly has two clock domains, namely XCLK and RXUSRCLK domains. The RX elastic buffer function is mainly used to match the phase difference between the two clocks.
If this RX elastic buffer is bypassed, certain conditions must be met to ensure stable data reception. First, a phase alignment circuit is needed to handle the phase difference between the SIPO circuit clock and the XCLK clock. Second, XCLK needs to be configured as the RXUSRCLK clock to ensure that XCLK and RXUSRCLK are in the same clock domain without phase difference.
RX Clock Correction: The “elastic” nature of the RX elastic buffer reflects the ability to adjust the frequency difference between XCLK and RXUSRCLK through clock correction. For the RX receiver, even if XCLK and RXUSRCLK run at the same clock frequency, there is often a certain difference. This difference can easily lead to the RX elastic buffer being either full or empty, necessitating the clock correction function. The clock correction function is shown in Figure 7.
Figure 7
In simple terms, at the TX transmitter, we periodically send K codes to ensure boundary alignment at the receiver. When the RX elastic buffer is low on data, the received K code data will be copied into the RX elastic buffer to keep it half full. When the RX elastic buffer has too much data, the received K code data will be discarded and not written into the RX elastic buffer to maintain it half full.
RX Channel Bonding: The channel bonding function also reflects the “elastic” aspect of the RX elastic buffer. For protocols like PCIE and SRIO, multi-lane transmission can be supported to increase total bandwidth. Due to the nature of the transmission channel, the data sent by the TX transmitter at the same time cannot be received by all lanes at the same time. Each lane has a time difference in receiving, so when recovering data, it needs to be realigned, which is why the channel bonding function needs to be executed at the RX receiver.
To achieve this function, the TX transmitter adds a corresponding channel bonding sequence in the data stream sent. The RX receiver adjusts and delays in each RX elastic buffer according to the detected channel bonding sequence on each lane, ultimately aligning the data from each lane so that the output of the FPGA RX Interface matches the data sent by the TX transmitter. This function is shown in Figure 8; the left side shows misaligned data, while the right side shows aligned data.
Figure 8
FPGA RX Interface: Users receive data through the FPGA RX Interface, similar to the TX transmitter. Data is received at the rising edge of RXUSRCLK2 (the TX transmitter sends data at the rising edge of TXUSRCLK2). This user port can be set to 16/20/32/40/64/80 bit widths, and the rate of RXUSRCLK2 is determined by the RX line rate, RXDATA bit width, and whether 8B/10B is enabled. The specific ports are shown in Table 1, and since they are similar to the TX, they will not be described further.
Table 1
At this point, the RX receiver introduction is complete. The next blog will introduce how to use the 7-Series Transceivers IP.
Next: Xilinx 7 Series FPGA High-Speed Transceiver Usage—Transceivers IP Usage
