Xilinx FPGA Configuration Process

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Although the configuration modes of FPGA vary, the overall workflow of FPGA during the configuration process is consistent, which can be divided into three parts: Setup, Load, and Start.

• Reset Ends, Configuration Begins

There are multiple ways to enter this configuration process for FPGA. At power-up, before the voltage reaches FPGA‘s requirements, the power-on reset module of FPGA will keep it in a reset state; an external control PROG_B pin receiving a low pulse can also keep FPGA in a reset state.

• Clear Configuration Storage Contents

This step is called initialization. When FPGA exits reset, the contents of the configuration memory will be automatically cleared. During this step, all FPGA I/O except for the configuration-specific interface are placed in a high-impedance state. During the entire initialization process, the INIT_B pin is pulled low and returns to a high level after initialization ends. If the INIT_B signal is pulled low externally, FPGA will remain in the initialization state. Note that the PROG_B signal pulse width cannot be too narrow.

• Sample Control Signals

After initialization ends, the INIT_B signal returns to high level. FPGA begins to sample the mode selection pins M[1:0] and variable selection pin VS. If in active mode, FPGA will quickly provide valid CCLK. The VS signal is only effective in active BPI and its SPI modes. At this point, FPGA begins to sample configuration data on the rising edge of the configuration clock.

• Synchronization

Each FPGA configuration data stream has a synchronization header, which is a special synchronization word. The synchronization word is mainly used to help FPGA determine the correct data position. Configuration data before the synchronization word will be ignored by FPGA, meaning that FPGA only formally starts receiving configuration data after synchronization. Generally, synchronization words consist of equal numbers of 0/1 binary digits, such as Spartan3 being AA995566.

• ID Check

After FPGA synchronizes, it will automatically check whether the device ID in the configuration stream matches the target device ID. This step ensures that FPGA is not misconfigured by an incorrect configuration stream.

A 32-bit ID contains 28 bits of feature values and 4 bits of mask. The feature values include vendor information, device family, device size, etc. When there is an issue with the device ID check, FPGA will set the first bit of the internal register ID_Err high, and the software will display an error message.

• Load Configuration Content

After the ID check passes smoothly, FPGA begins to load configuration data.

• CRC Check

During the data loading process, FPGA will perform a CRC check on each frame of data. If it fails, FPGA will pull the INIT_B signal low and terminate the configuration process.

• Start Sequence

After the configuration data is loaded, FPGA enters the start sequence. The default order of start sequence events is to first release the DONE pin, then activate the I/O, and finally start write enable. In actual use, the start order can be set through BitGen parameters to meet different needs.

Start Sequence Content	Stage	BitGen Options
Wait for DCM Lock	1~6	LCK_cycle
Wait for DCI Match	1~6	Match_cycle
Start Global Write Enable, Allow Internal Timing Elements to Flip	1~6	GWE_cycle
Release IO Tri-state, Activate IO	1~6	GTS_cycle
Release DONE Pin	1~6	DONE_cycle

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