Welcome FPGA engineers to join the official WeChat technical group. Fanout refers to the number of lower-level modules directly called by a module. If this value is too large, it directly manifests as a large net delay in FPGA, which is not conducive to timing convergence. Therefore, when writing code, one should try to avoid … Read more
✎ Author’s Note Recently, I worked on a project that had poor performance, and optimizing the timing was quite challenging. During the optimization process, I encountered a unique optimization related to the adder, which I would like to document. Issues with Reset Signal Fanout in Adders For reset signals in FPGA design, they are primarily … Read more
Two years ago, a previous article briefly introduced some basic knowledge of Multi-bit. For more details, please refer to: Exploring Multi-Bit FF in Chip Design. Based on this old article, there are still many technical details regarding MBFF (Multi-bit FF) that are worth learning and understanding again. Therefore, I will clarify the technical and process … Read more