1. Low Power Design
With the promotion of handheld portable devices, the issue of low power design has become increasingly important. Lower chip power consumption means longer usage time for portable devices, increased lifespan of chips due to reduced power consumption, better control of heat dissipation, and the ability to make devices smaller, among other benefits. Low power design is a holistic concept, meaning that power consumption can be optimized at every design level—algorithm level optimization, RTL code optimization, gate-level netlist optimization, layout optimization, etc. Moreover, the higher the abstraction level, the greater the degree of power optimization; for example, algorithm level optimization can reduce power consumption by more than 70%, while layout optimization may only achieve about 10% optimization.
There are many methods for low power design, which can be roughly divided into the following categories based on the author’s understanding: a. Multi-threshold process method: different circuit modules use basic gate-level circuits with different thresholds; b. Power gating: controlling the power of a certain part of the circuit through special logic gates, turning on the power of that circuit only when needed to reduce power consumption; c. Multi-voltage domains: different areas of circuit modules use different supply voltages; for example, circuits with high frequency use high voltage, while circuits with lower frequency use low voltage; d. Gated clock: using logic gates to control the stopping or starting of module clocks, gated clocks can be directly inserted through DC commands; e. Operand separation; f. Gate-level circuit optimization; g. Layout optimization; etc. For ASIC designers, the optimization methods vary depending on the job position. a-c are optimization methods for system-level designers, d-f are for RTL and gate-level designers, and g is an analytical method that layout personnel can master. These concepts are too broad; without personally participating in a project that applies low power technology, it is hard to have a deep understanding. For ASIC designers, it is difficult to fully grasp these low power technologies.
In the books recommended by the author, there are power optimization processes based on Power Compiler (belonging to DC) and PTPX (Prime Time-PX). The theoretical learning generally needs to understand that power consumption can be classified into: 1. Static power consumption – leakage power, 2. Dynamic power consumption – switching power, flip power, and total power consumption is the sum of the above three types of power. How does the software analyze these three types of power? The answer is still the technology library. In the synthesis library .lib file, many parameters are related to these three types of power, as shown below.
Leakage power of a certain cell:
cell_leakage_power : 330.503175;
leakage_power() {
when :”!A & !B & !CI”;
value : 318.529800;
}
leakage_power() {
when :”!A & !B & CI”;
value : 375.946200;
}
leakage_power() {
when :”!A & B & !CI”;
value : 347.668200;
}
leakage_power() {
when :”!A & B & CI”;
value : 309.481200;
}
leakage_power() {
when :”A & !B & !CI”;
value : 312.384600;
}
leakage_power() {
when :”A & !B & CI”;
value : 352.481400;
}
leakage_power() {
when :”A & B & !CI”;
value : 324.199800;
}
leakage_power() {
when :”A & B & CI”;
value : 303.334200;
}
Internal power consumption under the condition of a cell (!A & B) | (A & !B), rising edge, falling edge power:
internal_power() {
related_pin : “CI”;
equal_or_opposite_output : “CO”;
when : “(!A & B) | (A & !B)”;
rise_power(energy_template_7x3x3) {
index_1 (“0.03, 0.1, 0.4, 0.9, 1.5, 2.2, 3”);
index_2 (“0.00035, 0.0385, 0.3115”);
index_3 (“0.00035, 0.0385, 0.3115”);
values ( \\
“0.067236, 0.068853, 0.068513”, “0.071757, 0.070275, 0.070806”, “0.080913, 0.079223, 0.078953”, \\
“0.067380, 0.068914, 0.068524”, “0.071910, 0.070393, 0.070843”, “0.081073, 0.079343, 0.079093”, \\
“0.072993, 0.073749, 0.073240”, “0.077639, 0.075163, 0.075587”, “0.086943, 0.084212, 0.084302”, \\
“0.088698, 0.085346, 0.084064”, “0.090733, 0.087112, 0.086360”, “0.100492, 0.096672, 0.095842”, \\
“0.104666, 0.099420, 0.097897”, “0.105970, 0.100660, 0.100035”, “0.115422, 0.109742, 0.108342”, \\
“0.123420, 0.117165, 0.114921”, “0.125151, 0.118985, 0.116790”, “0.133612, 0.127112, 0.125132”, \\
“0.145380, 0.138042, 0.134921”, “0.147057, 0.139940, 0.136555”, “0.155522, 0.148222, 0.145332”);
}
fall_power(energy_template_7x3x3) {
index_1 (“0.03, 0.1, 0.4, 0.9, 1.5, 2.2, 3”);
index_2 (“0.00035, 0.0385, 0.3115”);
index_3 (“0.00035, 0.0385, 0.3115”);
values ( \\
“0.050492, 0.055945, 0.064903”, “0.053891, 0.055156, 0.063903”, “0.053922, 0.056074, 0.063853”, \\
“0.050468, 0.055859, 0.064843”, “0.053846, 0.055057, 0.063833”, “0.053880, 0.056027, 0.063783”, \\
“0.055162, 0.059927, 0.068953”, “0.058462, 0.058987, 0.067812”, “0.058500, 0.059918, 0.067832”, \\
“0.071414, 0.070694, 0.079333”, “0.069997, 0.069600, 0.078113”, “0.069993, 0.070503, 0.078113”, \\
“0.087095, 0.085894, 0.093292”, “0.085467, 0.084469, 0.091692”, “0.085322, 0.084670, 0.091722”, \\
“0.105947, 0.103948, 0.110322”, “0.104070, 0.102399, 0.108522”, “0.103914, 0.102131, 0.108572”, \\
“0.127727, 0.124621, 0.130342”, “0.125641, 0.122880, 0.128522”, “0.125412, 0.122591, 0.128302”);
}
}
The information is sourced from the previously provided SIMC technology library.
For more information on the contents of the synthesis library .lib file, please refer to “Digital IC System Design,” which will not be elaborated here.
This further validates what was mentioned in the previous article about the technology library: the synthesis library .lib file is indeed very important. Analyzing power consumption of RTL code and gate-level netlists using software requires the participation of these synthesis libraries to analyze and optimize the chip’s power consumption.
2. Recommended Books:
“Practical Tutorial on ASIC Design”
“SoC Design Methods and Implementation”
“Digital IC System Design”
“PTPX User Guide 2016”
3. Tools
During synthesis, preliminary optimization of the generated gate-level netlist can be performed using the built-in tool Power Compiler in DC, which enables power optimization functions through relevant commands. An example of using this tool can be found in “Practical Tutorial on ASIC Design.”
Gate-level netlist optimization tool, PrimeTime PX. An example of using this tool can be found in “PTPX User Guide 2016.”
4. Example
As low power related technologies have not yet been used, the understanding of the low power analysis process based on Power Compiler (belonging to DC) and PTPX (Prime Time-PX) software is limited. I will fill in this gap later.
