Subtle Yet Unrecognized Low Power Design Techniques: Stack Effect Continuing from the previous discussion: We previously explained low power design techniques such as Clock Gating and Data Gating. Both can reduce the dynamic power consumption of circuits. The former can turn off the input clock signal of certain modules when they are idle, thereby reducing … Read more
Leakage power consumption has increased with each generation of CMOS technology. This leakage power not only poses a serious challenge for battery-powered or portable products but is also becoming an issue that wired devices such as servers, routers, and set-top boxes must address. To reduce the total leakage power consumption of chips, it is best … Read more
In the power-off module, it may be required for the register to latch the data before shutdown or to restore the latched data after the power is turned on, which requires a special unit called the Retention Register. The retention register has two sets of registers: the Main Register and the shadow register, where the … Read more