“Low Power Design Techniques – Power Gating – Retention Register“ The previous section introduced low power methods in IC design, including Multi Vdd and Power Gating techniques. In the Multi Vdd technique, if modules in different voltage domains need to communicate, a Level Shifter must be introduced between them. For Power Gating design, an Isolation … Read more
Isolation Units The SALT project utilized several different isolation techniques. The initial version of SALT was completed before tools supported the automatic insertion of isolation units. Therefore, we manually inserted these cells in the RTL. The interface between the CPU and the cache is particularly critical for timing and requires careful design and timing analysis. … Read more
Signal Isolation Once we have resolved the design and control issues of the switch structure, the next question is to determine the isolation strategy. Each interface in the power gating area needs to be managed. We need to ensure that turning off the power in this area does not cause short-circuit currents at the inputs … Read more
The design of the power grid has a direct impact on chip performance and reliability. It is essential to ensure that the power grid provides sufficient power voltage to all transistors within the cells, allowing the chip to operate normally under all possible conditions within a certain noise tolerance. However, as technology shrinks, the threshold … Read more
Leakage power consumption has increased with each generation of CMOS technology. This leakage power not only poses a serious challenge for battery-powered or portable products but is also becoming an issue that wired devices such as servers, routers, and set-top boxes must address. To reduce the total leakage power consumption of chips, it is best … Read more
State Retention and Restoration Methods Continuing from the previous text Low Power Design Methods – Power Gating Design (Part 1) Low Power Design Methods – Power Gating Design (Part 2) Given the power switch structure and isolation strategy, power gating can be applied to logic blocks. However, unless a retention strategy is employed, all state … Read more
The technologies discussed in the previous chapter are mature. Engineers have been using them for some time, and design tools have supported them for many years. In this chapter, we begin to discuss more recent and proactive methods to reduce power: power gating and adaptive voltage scaling, these two techniques. Both of these techniques differ … Read more
This article was originally published in the Zhihu column [The Path of Digital IC Backend Engineers]. In the field of low power design, the most effective way to reduce power consumption is through power shutdown. This is because no matter how low the voltage, how small the current, how slow the speed, or how minimal … Read more
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With the development of the times, people have gradually started to design various types of chips, one of which is the popular low-power chip design. These chips not only help extend the battery life of devices but also reduce the likelihood of overheating and improve system stability. If you want to design low-power chips, then … Read more