Low Power Design Techniques – Power Gating – Retention Register

Low Power Design Techniques - Power Gating - Retention Register

“Low Power Design Techniques – Power Gating –

Retention Register“

The previous section introduced low power methods in IC design, including Multi Vdd and Power Gating techniques. In the Multi Vdd technique, if modules in different voltage domains need to communicate, a Level Shifter must be introduced between them. For Power Gating design, an Isolation Cell must be added at its next-level interface. If two low power techniques are used in the design, a Level Shifter with isolation function (with Enable or Clamp terminals) must be used, as shown in the figure below:

Low Power Design Techniques - Power Gating - Retention Register

All the Cells mentioned above belong to Always On (AO) Cells, and the Level Shifter must have two power supply pins.

Meanwhile, for Power Domains that can be shut down (like PD1 in Block1 shown above), after shutting down the power, all internal data will be lost. If you want to retain this data after power off, there are several methods:

1. Before power off, store internal data in external RAM and read the data back after power on;

2. Use a Retention Register in the Power Domain that can be shut down. Its internal structure is as follows; this register can save data to an internal Shadow Register before the power is turned off using the SAVE signal. After power on, the data can be restored from the Shadow Register to the Main Register using the RESTORE signal.

Low Power Design Techniques - Power Gating - Retention Register

Like various low power Cells mentioned earlier, the Shadow Register inside the Retention Register is also an Always On Cell and must have an Always On power source. Since it is Always On, to achieve low power goals, high-threshold MOS transistors are mainly used internally to reduce Leakage Power in Power Down mode.

Besides the Shadow Register, the other devices in the Retention Register use a power supply that can be shut down. For high performance and fast data recovery, the Main Register may also use low-threshold transistors.

Compared to conventional registers, the Retention Register is larger, generally about 20% larger than ordinary registers, and if the design robustness is better, it may even exceed 50%. However, compared to other solutions, the speed of data recovery after power on is very fast, and the operation is also simple.

References:

Synopsys Low-Power Flow UserGuide

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