Isolation Units
The SALT project utilized several different isolation techniques. The initial version of SALT was completed before tools supported the automatic insertion of isolation units. Therefore, we manually inserted these cells in the RTL.
The interface between the CPU and the cache is particularly critical for timing and requires careful design and timing analysis. We placed isolation units on all outputs from the CPU to the cache, but positioned them in the cache’s VDRAM area. This was convenient in the SALT design since the cache is always powered on, simplifying the power routing to the isolation units.
The VDRAM area has input isolation units instantiated as “generic library cells.” These are simply RTL wrappers that can be mapped to behavioral simulation models or specific technology clamp cells in the standard cell library’s “power management suite.” This approach provides explicit instantiation of cells on many critical path signals from the CPU core logic to memory (including clock and reset). Instantiating these cells in RTL allows for a clear understanding of the clock and critical signals that need to be carefully managed during the implementation process. Balancing the clocks between isolation units is not straightforward; isolation units often limit the flexibility of clock buffer tools in reconstructing the buffer tree.
The outputs from the CPU to the bus interface unit are isolated by units placed within the CPU (i.e., the VDDCPU area). These output isolation units pull down all output signals at the AMBA bus interface during sleep mode (local power gating) to ensure clean SOC interface signals.
However, when the CPU rail is turned off (in sleep mode), these isolation units lose their VDDCPU power, and the outputs may float again. To address this issue, simple bus repeaters or hold units were added in the VDDSOC domain to clamp these outputs while avoiding any further gate delays. Additionally, isolation control signals from the power controller drive resets in the bus interface module to force all bus interface protocol signals to a logic 0 clamp.
The power controller generates a single isolation control signal, but it is routed as two separate signals. One copy enters the cache RAM without passing through the CPU area, while another copy goes to the CPU without passing through the cache. When VDDCPU turns off its power rail during sleep, the isolation signal for the cache remains powered because all buffers in its path are powered by VDDSOC or VDDRAM. Therefore, the cache inputs are protected from floating signals (and data corruption) during sleep.
The USB OTG module uses an alternative instantiated AND gate unit in RTL and adds appropriate “no touch” attributes to prevent logical optimization across these isolation boundaries. During synthesis, we enforced mapping these AND gates to units that do not use a floating input (as long as the other input is low).
All isolation units in the SALT design are instantiated using generic, technology-independent packaging modules. This provides a degree of design portability for manually instantiated units and allows for simulation before selecting a specific technology library.
As mentioned above, the initial version of the SALT chip instantiated isolation units in RTL. In subsequent versions, we implemented isolation units using EDA tools without modifying the RTL. Repartitioning the CPU subsystem to include VDDSOC also eliminated the need for the AMBA bus to interface with bus repeater unit signals. Now, isolation units receive power from the always-on VDDSOC. Thus, a set of isolation units is used to isolate bus interface signals.
Using UPF-defined analog semantics, isolation units can be instantiated and simulated by issuing UPF TCL commands (set_isolation); manual instantiation or generic wrappers are not required.
Hold Units
The SALT project combines various hold techniques to compare and analyze the area/time/energy cost functions of each technology on the same chip.
The CPU uses full state retention. Given a well-validated CPU core, retaining each register bit state is the only safe way to ensure the processor can restart in any control state and data state. To retain only architectural state and use reset signals for non-architectural state would require serious validation efforts.
A key issue in any power gating design is ensuring that hold registers are not corrupted during the power down/power up sequence. In SALT, we added a non-real-time diagnostic mechanism for power control ordering. It uses a “sleep” scan function to checksum the contents of all shadow registers after a SAVE operation and saves it to external memory, then checksums and saves the entire register contents after a RESTORE operation. These can then be compared to detect any corruption of hold registers during power ordering.
This method allows for error analysis of random and location-sensitive issues as well as the effectiveness of soft-start power gating ordering in limiting surge currents. It has also proven to be a valuable method for quantifying the safety margin of hold triggers, allowing them to withstand thermal and voltage shocks in hold mode.
On the other hand, the USB OTG core uses partial retention. The core is partitioned to retain persistent USB endpoint data stored in the control and status register (CSR) block, while the protocol interface engine (PIE) block contains only protocol state. The data for the current transaction is stored in a RAM-based FIFO. During power down, USB waits for the current transaction to complete, so the FIFO is empty. Standard hold register techniques are then used to save all states of the CSR. Upon power up, the CSR restores its state and issues a reset signal to the PIE. This resets the protocol engine and prepares it for the next transaction.
Inferring Power Gating and Hold
In the SALT project, we use hold register units with single-pin control to manage save and restore edge-triggered behavior. The hold state is captured on the falling edge of the NRETAIN signal, which is active low, and restored on the rising edge of NRETAIN:
We can modify UPF to display this hold behavior as follows:
