“Low Power Design Techniques – Power Gating – Retention Register“ The previous section introduced low power methods in IC design, including Multi Vdd and Power Gating techniques. In the Multi Vdd technique, if modules in different voltage domains need to communicate, a Level Shifter must be introduced between them. For Power Gating design, an Isolation … Read more
In multi-voltage design, isolation cells are often used. This article briefly introduces what an iso cell is, how to use an iso cell, when to add an iso cell, and the insertion position of the iso cell. 1. What is an iso cell? An isolation cell, typically used in Power Shutdown (PSO) and Multi-Supply Multi-Voltage … Read more
In the previous article, we introduced methods forsystem-level low power design, such ashardware-software co-design,power management mechanisms, etc. This issue will delve into the core technologies ofarchitecture-level low power design, includingmulti-voltage design (Multi-VDD),dynamic voltage frequency scaling (DVFS),system clock optimization,asynchronous design, andalgorithm optimization. By reasonably dividing power supply areas, dynamically adjusting voltage and frequency, and optimizing clock … Read more
We know that typical IC components usually have only two power pins, one is Vcc or Vdd, and the other is Gnd or Vss. However, modern MCUs often have multiple power pins; what is the reason for this? Taking a 100-pin MCU as an example, we can see that it has 5 sets of VDD/VSS, … Read more
We all know that typical IC components usually have two power pins, one is Vcc or Vdd, and the other is Gnd or Vss. However, modern MCUs often have multiple power pins. What is the reason for this?Taking a 100-pin MCU as an example, as shown in the figure below, we can see that it … Read more