In FPGA (Field Programmable Gate Array) interviews, questions typically revolve around fundamental principles, design processes, hardware description languages, timing analysis, and practical applications. 1. Basic Concepts and Structure What is the difference between FPGA and CPLD? Structure: FPGA is centered around CLB (Configurable Logic Block), containing numerous LUTs (Look-Up Tables) and registers, with abundant routing … Read more
1. Hardware Circuit Design (Basic Assurance) Power Supply and Ripple Control The core power supply (e.g., 1.2V for DDR4) should be independently powered, paired with a capacitor array of 10μF + 0.1μF, with ripple control within ±5%; Termination resistors (ODT) should be placed close to the DDR chips, with matched impedance (typically 50Ω/60Ω) to reduce … Read more
Click the blue text to follow, grateful for your support Welcome friends to follow the “Hao Xushuang Electronic Design Team” public account. This account will regularly update relevant technical materials, software, etc. Friends who are interested can browse other “modules” of this public account, hoping that everyone can gain something they desire from this public … Read more
Overview The Xilinx white paper WP272 “Get Smart About Reset: Think Local, Not Global” details the global reset of FPGAs. In digital system design, we traditionally believe that a reset signal should be set for all flip-flops, which greatly facilitates subsequent testing. Therefore, when the document mentions that “global reset is not recommended in FPGA … Read more
Master the correct learning path, bridging the gap between theory and practice from development boards to project implementation. In recent years, with the rise of artificial intelligence, 5G communication, and heterogeneous computing, the demand for FPGA engineers has been continuously increasing. Many students and engineers in electronic engineering and microelectronics hope to enter this field … Read more
“Deeply cultivate the market, pursue excellence” XINLITONG 16862A 68-Channel Portable Logic Analyzer Suzhou Xinlitong Overview 68-Channel Portable Logic Analyzer The 16862A Portable Logic Analyzer provides faster deep memory timing capture capabilities, helping you complete digital debugging more quickly. Features Logic Analyzer Configuration Standard 68 channels, 350 MHz state, 12.5 GHz timing scaling, 2.5 GHz timing, … Read more
InXilinx FPGA, the Site is the smallest configurable unit in the physical layout of the chip, representing the specific location of hardware resources. 1. Definition and Function of Site Physical Level: A Site is the smallest independently configurable unit on an FPGA chip, with each Site corresponding to a fixed physical location, containing specific resources … Read more
Level ShiftersLevel shifters – converting voltage from low to high Driving logic signals from a low power rail to a high voltage rail is a critical issue. Under-driven signals can lead to degraded rise and fall times at the receiving end. This, in turn, can result in higher switching short-circuit currents and reduced noise margins. … Read more
During the process of FPGA design, it is common to encounter warnings during compilation indicating that some latches have been generated. Generally, the design rules for FPGAs also advise against the generation of latches. So, what exactly is a latch? And how can we avoid the occurrence of latches in FPGA design?1 Comparison of Latches, … Read more
The technologies discussed in the previous chapter are mature. Engineers have been using them for some time, and design tools have supported them for many years. In this chapter, we begin to discuss more recent and proactive methods to reduce power: power gating and adaptive voltage scaling, these two techniques. Both of these techniques differ … Read more