Author: Clive “Max” Maxfield
Introduction to Xilinx FPGA, SoC, MPSoC, RFSoC, and ACAP Products
Xilinx offers a wide variety of programmable device products, with performance and functionality ranging from medium to very high. The range includes traditional FPGAs, SoCs (FPGA programmable structures with a single hard core processor), MPSoCs (FPGA programmable structures with multiple hard core processors), RFSoCs (MPSoCs with RF capabilities), and ACAPs (Adaptive Compute Acceleration Platforms) (Figure 2).
Figure 2: Over time, the Xilinx architecture product portfolio has evolved from simple FPGAs that only contain programmable structures to SoC devices enhanced with hard core processors, MPSoCs with multiple processors, RFSoCs with RF capabilities, and the latest generation of ACAPs for applications such as AI. (Image source: Max Maxfield)
Xilinx has a very broad product portfolio that covers many market segments and offers various deployment methods, making it difficult for newcomers to FPGAs to understand the “big picture”.
Xilinx’s market segments include, but are not limited to, data centers (compute, networking, storage); communications (wired, wireless); aerospace and defense; industrial, scientific, and medical (ISM); test, measurement, and emulation (TME); as well as automotive, broadcast, and consumer products.
As for deployment methods, these include what Xilinx refers to as hardware adaptive devices, which include chips, evaluation boards, and development kits; deployable end systems, including system on modules (SoMs) and PCIe accelerator cards; and FPGA as a Service (FAAS), which allows evaluation and utilization of Xilinx technology through leading cloud providers (including Amazon Web Services [AWS], Alibaba.com, and Nimbix.net).
For Xilinx’s FPGA products, one classification method is based on process technology nodes (Figure 3).
Figure 3: Xilinx’s FPGA products offer a comprehensive multi-node product portfolio to meet the needs of various applications. (Image source: Max Maxfield)
Depending on the target application, designers can choose to implement low-cost, small footprint FPGAs based on earlier technology nodes, or select high-capacity, high-bandwidth, high-performance devices based on the latest technology nodes for applications such as networking.
For designs requiring one or more hard processor cores (as well as additional enhanced features such as GPUs, codecs, and soft decision forward error correction [SD-FEC] cores), Xilinx offers a device product portfolio named Zynq. A summary of Zynq’s SoC, MPSoC, and RFSoC products is shown in Figure 4. This solution offers designers a wide range of capabilities to help optimize power consumption, performance, cost, and time to market.
Figure 4: Xilinx’s SoC, MPSoC, and RFSoC products integrate the software programmability of processors with the hardware programmability of FPGAs, providing designers with system performance, flexibility, and scalability. (Image source: Max Maxfield)
Xilinx’s latest product is the Versal Adaptive Compute Acceleration Platform (ACAP), all of which are based on a 7-nanometer (nm) process technology node. ACAP is a highly integrated multi-core computing platform that can adapt to a variety of evolving algorithms. They can be dynamically customized at both hardware and software levels to suit various applications and workloads. ACAP is built around a programmable network on chip (NoC), allowing hardware designers and software developers to easily program it.
The new features of Versal devices include intelligent engines, which are large-scale vector processor arrays for ML and DSP workloads; a high-bandwidth, low-latency, low-power programmable NoC that can move TB-level data; and an integrated shell that enhances performance, utilization, and productivity through pre-built core infrastructure and system connectivity.
Figure 5 provides an overview of the Versal ACAP product portfolio.
Figure 5: Xilinx’s Versal ACAP is a highly integrated multi-core computing platform that can adapt to a variety of evolving algorithms. ACAP can be dynamically customized at both hardware and software levels to suit various applications and workloads. (Image source: Max Maxfield)
As will be discussed in the design tools section, a key distinction regarding Versal devices is the new software stack. This stack is primarily aimed at data scientists and software engineers, as well as traditional hardware design engineers.
There are a variety of Xilinx devices available on the market. Some representative products are the Artix-7 FPGA, Kintex UltraScale FPGA, Kintex UltraScale+ FPGA, Zynq-7000 SoC module from Trenz Electronic GmbH, and Zynq UltraScale+ MPSoC.
Similarly, there are a variety of evaluation boards and development boards available. Some representative products include the Artix-7 FPGA evaluation board from Digilent, the Kintex UltraScale FPGA evaluation board from Analog Devices, the Kintex UltraScale+ FPGA evaluation board from Xilinx, the Zynq-7000 SoC FPGA evaluation board from Digilent, and the Zynq UltraScale+ MPSoC FPGA evaluation board from Xilinx.
Designing and Developing with Xilinx’s FPGA, SoC, and ACAP
One factor that truly sets Xilinx apart from competitors is the breadth and depth of its design tools and processes.
In part 1 of this FPGA series, we noted that the traditional design approach for these devices is for engineers to use hardware description languages (HDLs) such as Verilog or VHDL to capture design intent at the abstract level (i.e., register transfer level [RTL]). These RTL descriptions can first be simulated to verify that they meet requirements, and then passed to synthesis tools to generate configuration files for programming the FPGA.
The next step of abstraction is to capture design intent primarily using programming languages like C/C++ or special implementation tools like SystemC; the latter is a set of C++ classes and macros that provide an event-driven simulation interface. These methods facilitate the simulation of concurrent processes, with each process being described using simple C++ syntax. Such descriptions can be analyzed and configured by running them like conventional programs, and then passed to a high-level synthesis (HLS) engine, which outputs RTL that is then passed to a conventional synthesis engine.
All these capabilities are included in the Vivado Design Suite HLx edition, whose output is a configuration bitstream that is subsequently loaded into the target FPGA, SoC, MPSoC, RFSoC, or ACAP device. In addition to allowing hardware developers to leverage C-based designs and optimized design reuse, Vivado also provides IP subsystem reuse, integrated automation, and accelerated design convergence capabilities (Figure 6).
Figure 6: A high-level view of Xilinx’s Vivado and Vitis design tool stack reflects how users can use these tools at the most appropriate level of abstraction. Hardware designers use Vivado, software developers use Vitis, and AI and data scientists use Vitis AI. (Image source: Max Maxfield)
The next level of abstraction is supported by the Vitis Unified Software Platform, which allows software developers to seamlessly build accelerated applications. Conceptually, above Vitis is Vitis AI, which allows AI and data scientists to work at the TensorFlow abstraction level. Vitis AI is a development platform for AI inference on Xilinx hardware platforms, including both edge devices and Alveo PCIe cards. This platform consists of optimized IP, tools, libraries, models, and example designs, all designed to maximize the AI acceleration potential on Xilinx’s FPGAs and ACAP devices.
Vitis AI feeds into Vitis, and Vitis itself feeds into Vivado. The key point in Figure 6 is that users only “see” what they need to “see”. That is, hardware developers will only “see” Vivado, software developers will only “see” Vitis, and AI and data scientists will only “see” Vitis AI. This way, users can use these tools at the most appropriate level of abstraction.
By providing software development tools like Vitis, which isolate them from the underlying hardware, FPGA can be opened up to more developers. Similarly, by providing tools like Vitis AI for AI and data scientists, allowing them to focus on their abstraction level and isolate it from the underlying software, FPGAs can be opened up to new groups of developers.
Xilinx is at the forefront of providing these capabilities across the industry, committed to elevating FPGA tools to higher design abstraction levels, which will enable developers to more easily leverage the capabilities of these devices and integrate them into their next designs.
Conclusion
The best design solution is often provided by a combination of processors and FPGAs, or solely by FPGAs, or by FPGAs with hard processor cores as part of the structure. As a technology, FPGAs have rapidly evolved over the years to meet various design requirements for flexibility, processing speed, and power consumption, making them ideal for a wide range of applications such as smart interfaces, machine vision, and artificial intelligence.
As mentioned above, Xilinx offers many programmable device products, with performance and functionality ranging from medium to very high. These products range from traditional FPGAs to SoCs (FPGA programmable structures with a single hard core processor), MPSoCs (FPGA programmable structures with multiple hard core processors), RFSoCs (MPSoCs with RF capabilities), and ACAPs (Adaptive Compute Acceleration Platforms).
To assist designers in using these devices to construct designs, Xilinx provides a suite of tools to meet the needs of hardware developers (Vivado), software developers (Vitis), and AI and data scientists (Vitis AI).
